公开(公告)号：US20150035025A1

公开(公告)日：2015-02-05

申请号：US14516201

申请日：2014-10-16

申请人： Bong-Soo KIM ,  Soo-Ho SHIN ,  Ho-In RYU ,  Hyeong-Sun HONG

发明人： Bong-Soo KIM ,  Soo-Ho SHIN ,  Ho-In RYU ,  Hyeong-Sun HONG

IPC分类号： H01L29/78 ,  H01L27/108

CPC分类号： H01L29/78 ,  H01L27/0207 ,  H01L27/10805 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/10897 ,  H01L29/7833

摘要： Provided are semiconductor integrated circuit (IC) devices including gate patterns having a step difference therebetween and a connection line interposed between the gate patterns. The semiconductor IC device includes a semiconductor substrate including a peripheral active region, a cell active region, and a device isolation layer. Cell gate patterns are disposed on the cell active region and the device isolation layer. A peripheral gate pattern is disposed on the peripheral active region. A cell electrical node is disposed on the cell active region adjacent to the cell gate patterns. Peripheral electrical nodes are disposed on the peripheral active region adjacent to the peripheral gate pattern. Connection lines are disposed on the cell gate patterns disposed on the device isolation layer. The connection lines are connected between the cell gate patterns and the peripheral gate pattern.

摘要翻译： 提供了包括其间具有台阶差的栅极图案和插入在栅极图案之间的连接线的半导体集成电路（IC）装置。 半导体IC器件包括包括外围有源区，单元有源区和器件隔离层的半导体衬底。 单元栅极图案设置在单元有源区和器件隔离层上。 外围栅极图案设置在外围有源区域上。 电池电节点设置在与电池栅极图案相邻的电池有源区域上。 外围电节点设置在与外围栅极图案相邻的外围有源区域上。 连接线设置在设置在器件隔离层上的单元栅极图案上。 连接线连接在单元栅极图案和外围栅极图案之间。

公开(公告)号：US08766354B2

公开(公告)日：2014-07-01

申请号：US13185961

申请日：2011-07-19

申请人： Hyun-woo Chung ,  Hyeong-sun Hong ,  Yong-chul Oh ,  Yoo-sang Hwang ,  Cheol-ho Baek ,  Kang-uk Kim

发明人： Hyun-woo Chung ,  Hyeong-sun Hong ,  Yong-chul Oh ,  Yoo-sang Hwang ,  Cheol-ho Baek ,  Kang-uk Kim

IPC分类号： H01L29/66

CPC分类号： H01L27/10876 ,  H01L27/10882 ,  H01L27/10885 ,  H01L27/10891 ,  H01L29/66666 ,  H01L29/7827

摘要： A semiconductor device including a plurality of buried word lines extending in a first direction and a plurality of buried bit lines extending in a second direction. Upper surfaces of the plurality of buried word lines and the plurality of buried bit lines are lower than an upper surface of a substrate. The distance between two active regions that constitute a pair of first active regions from among a plurality of first active regions included in a first group of active regions is less than the distance between two adjacent active regions having the plurality of buried bit lines therebetween. A method of manufacturing a semiconductor device includes forming a plurality of first trenches in a substrate, forming a plurality of first conductive patterns in the plurality of first trenches in such a manner that a pair of first conductive patterns is disposed in each of the plurality of first trenches, forming a plurality of first buried patterns in the plurality of first trenches to cover the plurality of first conductive patterns, forming a plurality of second trenches by etching the substrate between the plurality of first trenches, and forming a plurality of second buried patterns in the plurality of second trenches.

摘要翻译： 一种半导体器件，包括沿第一方向延伸的多个掩埋字线和沿第二方向延伸的多个掩埋位线。 多个掩埋字线和多个掩埋位线的上表面比衬底的上表面低。 构成第一组有源区域中的多个第一有源区域中的构成一对第一有源区域的两个有源区域之间的距离小于其间具有多个掩埋位线的两个相邻有源区域之间的距离。 一种制造半导体器件的方法包括在衬底中形成多个第一沟槽，在多个第一沟槽中形成多个第一导电图案，使得一对第一导电图案设置在多个第一沟槽中的每一个中 第一沟槽，在所述多个第一沟槽中形成多个第一掩埋图案以覆盖所述多个第一导电图案，通过在所述多个第一沟槽之间蚀刻所述衬底形成多个第二沟槽，以及形成多个第二掩埋图案 在多个第二沟槽中。

公开(公告)号：US08742493B2

公开(公告)日：2014-06-03

申请号：US13285263

申请日：2011-10-31

申请人： Dae-Ik Kim ,  Hyeong-Sun Hong ,  Yoo-Sang Hwang ,  Hyun-Woo Chung

发明人： Dae-Ik Kim ,  Hyeong-Sun Hong ,  Yoo-Sang Hwang ,  Hyun-Woo Chung

IPC分类号： H01L27/108

CPC分类号： H01L29/7827 ,  H01L27/10876 ,  H01L29/1033 ,  H01L29/1087 ,  H01L29/66666 ,  H01L29/7831

摘要： A semiconductor device has a plurality of vertical channels extending upright on a substrate, a plurality of bit lines extending among the vertical channels, a plurality of word lines which include a plurality of gates disposed adjacent first sides of the vertical channels, respectively, and a plurality of conductive elements disposed adjacent second sides of the vertical channels opposite the first sides. The conductive elements can provide a path to the substrate for charge carriers which have accumulated in the associated vertical channel to thereby mitigate a so-called floating effect.

摘要翻译： 半导体器件具有在基板上竖直延伸的多个垂直通道，在垂直通道之间延伸的多个位线，分别包括与垂直通道的第一侧相邻设置的多个栅极的多条字线，以及 多个导电元件设置在与第一侧相对的垂直通道的第二侧附近。 导电元件可以提供到已经累积在相关联的垂直通道中的电荷载体的衬底的路径，从而减轻所谓的浮动效应。

公开(公告)号：US20130115745A1

公开(公告)日：2013-05-09

申请号：US13607315

申请日：2012-09-07

申请人： Hyun-woo Chung ,  Hyeong-sun Hong ,  Yoo-sang Hwang ,  Ji-young Kim ,  Jay-bok Choi

发明人： Hyun-woo Chung ,  Hyeong-sun Hong ,  Yoo-sang Hwang ,  Ji-young Kim ,  Jay-bok Choi

IPC分类号： H01L21/336

CPC分类号： H01L27/10876

摘要： Methods of manufacturing a semiconductor device can be provided by forming a structure including a plurality of gate trenches that extend in a first direction and a mold layer having openings and that extend in the first direction on a substrate. Filling layers can be formed to fill the openings and the mold layer can be removed so that the filling layers remain on the substrate. A spacer layer can be formed which fills a space between the filling layers directly adjacent to each other at one side of each of the filling layers and forms a spacer at the sidewall of each of the filling layers at the other side of each of the filling layers. Device isolation trenches can be formed that extend in parallel to the plurality of gate trenches by etching the substrate exposed by the spacer layer.

摘要翻译： 制造半导体器件的方法可以通过形成包括在第一方向上延伸的多个栅极沟槽和具有开口并且在基板上沿第一方向延伸的模具层的结构来提供。 可以形成填充层以填充开口，并且可以去除模具层，使得填充层保留在基底上。 可以形成间隔层，其在每个填充层的一侧填充彼此直接相邻的填充层之间的空间，并且在每个填充层的另一侧的每个填充层的侧壁处形成间隔物 层。 可以通过蚀刻由间隔层暴露的衬底来形成平行于多个栅极沟槽延伸的器件隔离沟槽。

公开(公告)号：US20120299090A1

公开(公告)日：2012-11-29

申请号：US13298644

申请日：2011-11-17

申请人： Ji-Young Kim ,  Gyo-Young Jin ,  Hyeong-Sun Hong ,  Yong-Chul Oh ,  Yoo-Sang Hwang ,  Sung-Kwan Choi ,  Dong-Soo Woo ,  Hyun-Woo Chung

发明人： Ji-Young Kim ,  Gyo-Young Jin ,  Hyeong-Sun Hong ,  Yong-Chul Oh ,  Yoo-Sang Hwang ,  Sung-Kwan Choi ,  Dong-Soo Woo ,  Hyun-Woo Chung

IPC分类号： H01L29/78

CPC分类号： G11C11/4096 ,  G11C11/404 ,  G11C11/4085 ,  H01L21/823437 ,  H01L27/10823 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10891 ,  H01L27/10894 ,  H01L29/41741 ,  H01L29/4236 ,  H01L29/66484 ,  H01L29/66613 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/7831

摘要： A semiconductor device may include a semiconductor substrate with first and second spaced apart source/drain regions defining a channel region therebetween and a control gate structure on the channel region between the first and second spaced apart source/drain regions. More particularly, the control gate structure may include a first gate electrode on the channel region adjacent the first source/drain region, and a second gate electrode on the channel region adjacent the second source/drain region. Moreover, the first and second gate electrodes may be electrically isolated. Related devices, structures, methods of operation, and methods of fabrication are also discussed.

摘要翻译： 半导体器件可以包括具有限定其间的沟道区的第一和第二间隔开的源极/漏极区的半导体衬底，以及在第一和第二间隔开的源极/漏极区之间的沟道区上的控制栅极结构。 更具体地，控制栅极结构可以包括在与第一源极/漏极区域相邻的沟道区域上的第一栅极电极以及与第二源极/漏极区域相邻的沟道区域上的第二栅极电极。 此外，第一和第二栅电极可以是电隔离的。 还讨论了相关设备，结构，操作方法和制造方法。

公开(公告)号：US20110284939A1

公开(公告)日：2011-11-24

申请号：US12904344

申请日：2010-10-14

申请人： Hyung-woo Chung ,  Yong-chul OH ,  Yoo-sang HWANG ,  Gyo-young JIN ,  Hyeong-sun HONG ,  Dae-ik KIM

发明人： Hyung-woo Chung ,  Yong-chul OH ,  Yoo-sang HWANG ,  Gyo-young JIN ,  Hyeong-sun HONG ,  Dae-ik KIM

IPC分类号： H01L27/108

CPC分类号： H01L27/10805 ,  H01L27/0207 ,  H01L27/10876 ,  H01L27/10885

摘要： A semiconductor memory device includes a first pair of pillars extending from a substrate to form vertical channel regions, the first pair of pillars having a first pillar and a second pillar adjacent to each other, the first pillar and the second pillar arranged in a first direction, a first bit line disposed on a bottom surface of a first trench formed between the first pair of pillars, the first bit line extending in a second direction that is substantially perpendicular to the first direction, a first contact gate disposed on a first surface of the first pillar with a first gate insulating layer therebetween, a second contact gate disposed on a first surface of the second pillar with a second gate insulating layer therebetween, the first surface of the first pillar and the first surface of the second pillar face opposite directions, and a first word line disposed on the first contact gate and a second word line disposed on the second contact gate, the word lines extending in the first direction.

摘要翻译： 半导体存储器件包括从衬底延伸以形成垂直沟道区的第一对柱，所述第一对柱具有彼此相邻的第一柱和第二柱，所述第一柱和第二柱以第一方向 ，设置在形成在所述第一对柱之间的第一沟槽的底表面上的第一位线，所述第一位线在基本上垂直于所述第一方向的第二方向上延伸;第一接触栅极，设置在第一表面上， 所述第一支柱具有第一栅极绝缘层，第二触点栅极，设置在所述第二支柱的第一表面上，第二栅极绝缘层之间具有第二栅极绝缘层，所述第一支柱的第一表面和所述第二支柱的第一表面面向相反方向 以及设置在第一接触栅极上的第一字线和设置在第二接触栅极上的第二字线，在fi 第一个方向。

公开(公告)号：US07777265B2

公开(公告)日：2010-08-17

申请号：US11933039

申请日：2007-10-31

申请人： Hyeong-Sun Hong ,  Jae-Goo Lee ,  Dong-Hyun Kim ,  Sung-Un Kwon ,  Sang-Joon Park ,  Nam-Jung Kang

发明人： Hyeong-Sun Hong ,  Jae-Goo Lee ,  Dong-Hyun Kim ,  Sung-Un Kwon ,  Sang-Joon Park ,  Nam-Jung Kang

IPC分类号： H01L27/108

CPC分类号： H01L27/0207 ,  H01L21/76802 ,  H01L27/10808 ,  H01L27/10855 ,  H01L27/10885 ,  Y10S257/905

摘要： A semiconductor device having a contact barrier for insulating contacts with a large aspect ratio and having a fine pitch between adjacent conductive lines and a method of manufacturing the same are provided. The semiconductor device includes a buried contact formed in a region between two adjacent first conductive lines and two adjacent second conductive lines. Insulating lines define a width of the buried contact. To form the contact barrier, an interlayer dielectric layer formed on the second conductive lines is patterned to form a space and an insulating line having an etching ratio different from the interlayer dielectric layer is formed in the space. The interlayer dielectric layer is selectively wet etched relative to an insulating layer covering the second conductive line and the first insulating line to form buried contact hole. The buried contact hole is filled with conductive material to form a buried contact.

摘要翻译： 提供一种半导体器件，其具有用于具有大纵横比的绝缘触点的接触屏障，并且在相邻的导线之间具有微细的间距及其制造方法。 半导体器件包括形成在两个相邻的第一导电线和两个相邻的第二导电线之间的区域中的掩埋接触。 绝缘线限定埋入触点的宽度。 为了形成接触屏障，形成在第二导线上的层间电介质层形成空间，并且在该空间中形成具有与层间电介质层不同的蚀刻比的绝缘线。 相对于覆盖第二导线和第一绝缘线的绝缘层选择性地湿蚀刻层间电介质层以形成掩埋接触孔。 埋入的接触孔填充有导电材料以形成掩埋接触。

公开(公告)号：US08884340B2

公开(公告)日：2014-11-11

申请号：US13298644

申请日：2011-11-17

申请人： Ji-Young Kim ,  Gyo-Young Jin ,  Hyeong-Sun Hong ,  Yong-Chul Oh ,  Yoo-Sang Hwang ,  Sung-Kwan Choi ,  Dong-Soo Woo ,  Hyun-Woo Chung

发明人： Ji-Young Kim ,  Gyo-Young Jin ,  Hyeong-Sun Hong ,  Yong-Chul Oh ,  Yoo-Sang Hwang ,  Sung-Kwan Choi ,  Dong-Soo Woo ,  Hyun-Woo Chung

IPC分类号： H01L21/336 ,  H01L29/772 ,  G11C11/404 ,  H01L27/108 ,  H01L29/66 ,  H01L29/78 ,  G11C11/408 ,  H01L29/417 ,  H01L29/423 ,  H01L21/8234

CPC分类号： G11C11/4096 ,  G11C11/404 ,  G11C11/4085 ,  H01L21/823437 ,  H01L27/10823 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10891 ,  H01L27/10894 ,  H01L29/41741 ,  H01L29/4236 ,  H01L29/66484 ,  H01L29/66613 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/7831

摘要： A semiconductor device may include a semiconductor substrate with first and second spaced apart source/drain regions defining a channel region therebetween and a control gate structure on the channel region between the first and second spaced apart source/drain regions. More particularly, the control gate structure may include a first gate electrode on the channel region adjacent the first source/drain region, and a second gate electrode on the channel region adjacent the second source/drain region. Moreover, the first and second gate electrodes may be electrically isolated. Related devices, structures, methods of operation, and methods of fabrication are also discussed.

摘要翻译： 半导体器件可以包括具有限定其间的沟道区的第一和第二间隔开的源极/漏极区的半导体衬底，以及在第一和第二间隔开的源极/漏极区之间的沟道区上的控制栅极结构。 更具体地，控制栅极结构可以包括在与第一源极/漏极区域相邻的沟道区域上的第一栅极电极以及与第二源极/漏极区域相邻的沟道区域上的第二栅极电极。 此外，第一和第二栅电极可以是电隔离的。 还讨论了相关设备，结构，操作方法和制造方法。

公开(公告)号：US08872262B2

公开(公告)日：2014-10-28

申请号：US12781859

申请日：2010-05-18

申请人： Bong-Soo Kim ,  Hyeong-Sun Hong ,  Soo-Ho Shin ,  Ho-In Ryu

发明人： Bong-Soo Kim ,  Hyeong-Sun Hong ,  Soo-Ho Shin ,  Ho-In Ryu

IPC分类号： H01L27/108 ,  H01L27/02 ,  H01L29/78

CPC分类号： H01L29/78 ,  H01L27/0207 ,  H01L27/10805 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/10897 ,  H01L29/7833

摘要： Provided are semiconductor integrated circuit (IC) devices including gate patterns having a step difference therebetween and a connection line interposed between the gate patterns. The semiconductor IC device includes a semiconductor substrate including a peripheral active region, a cell active region, and a device isolation layer. Cell gate patterns are disposed on the cell active region and the device isolation layer. A peripheral gate pattern is disposed on the peripheral active region. A cell electrical node is disposed on the cell active region adjacent to the cell gate patterns. Peripheral electrical nodes are disposed on the peripheral active region adjacent to the peripheral gate pattern. Connection lines are disposed on the cell gate patterns disposed on the device isolation layer. The connection lines are connected between the cell gate patterns and the peripheral gate pattern.

摘要翻译： 提供了包括其间具有台阶差的栅极图案和插入在栅极图案之间的连接线的半导体集成电路（IC）装置。 半导体IC器件包括包括外围有源区，单元有源区和器件隔离层的半导体衬底。 单元栅极图案设置在单元有源区和器件隔离层上。 外围栅极图案设置在外围有源区域上。 电池电节点设置在与电池栅极图案相邻的电池有源区域上。 外围电节点设置在与外围栅极图案相邻的外围有源区域上。 连接线设置在设置在器件隔离层上的单元栅极图案上。 连接线连接在单元栅极图案和外围栅极图案之间。

公开(公告)号：US08362536B2

公开(公告)日：2013-01-29

申请号：US12904344

申请日：2010-10-14

申请人： Hyung-woo Chung ,  Yong-chul Oh ,  Yoo-sang Hwang ,  Gyo-young Jin ,  Hyeong-sun Hong ,  Dae-ik Kim

发明人： Hyung-woo Chung ,  Yong-chul Oh ,  Yoo-sang Hwang ,  Gyo-young Jin ,  Hyeong-sun Hong ,  Dae-ik Kim

IPC分类号： H01L27/108 ,  H01L29/94

CPC分类号： H01L27/10805 ,  H01L27/0207 ,  H01L27/10876 ,  H01L27/10885

摘要： A semiconductor memory device includes a first pair of pillars extending from a substrate to form vertical channel regions, the first pair of pillars having a first pillar and a second pillar adjacent to each other, the first pillar and the second pillar arranged in a first direction, a first bit line disposed on a bottom surface of a first trench formed between the first pair of pillars, the first bit line extending in a second direction that is substantially perpendicular to the first direction, a first contact gate disposed on a first surface of the first pillar with a first gate insulating layer therebetween, a second contact gate disposed on a first surface of the second pillar with a second gate insulating layer therebetween, the first surface of the first pillar and the first surface of the second pillar face opposite directions, and a first word line disposed on the first contact gate and a second word line disposed on the second contact gate, the word lines extending in the first direction.

摘要翻译： 半导体存储器件包括从衬底延伸以形成垂直沟道区的第一对柱，所述第一对柱具有彼此相邻的第一柱和第二柱，所述第一柱和第二柱以第一方向 ，设置在形成在所述第一对柱之间的第一沟槽的底表面上的第一位线，所述第一位线在基本上垂直于所述第一方向的第二方向上延伸;第一接触栅极，设置在第一表面上， 所述第一支柱具有第一栅极绝缘层，第二触点栅极，设置在所述第二支柱的第一表面上，第二栅极绝缘层之间具有第二栅极绝缘层，所述第一支柱的第一表面和所述第二支柱的第一表面面向相反方向 以及设置在第一接触栅极上的第一字线和设置在第二接触栅极上的第二字线，在fi 第一个方向。