公开(公告)号：US09601420B2

公开(公告)日：2017-03-21

申请号：US14018709

申请日：2013-09-05

Applicant: Yoo-Sang Hwang ,  Hyun-Woo Chung ,  Dae-Ik Kim

Inventor： Yoo-Sang Hwang ,  Hyun-Woo Chung ,  Dae-Ik Kim

IPC: H01L21/768 ,  H01L23/498 ,  H01L23/522 ,  H01L27/108 ,  H01L23/532 ,  H01L21/762

CPC classification number: H01L23/49811 ,  H01L21/76229 ,  H01L21/7682 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/522 ,  H01L23/5222 ,  H01L23/53295 ,  H01L27/10885 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a stack structure of a conductive line and an insulating capping line extending in a first direction on a substrate, a plurality of contact plugs arranged in a row along the first direction and having sidewall surfaces facing the conductive line with air spaces between the sidewall surfaces and the conductive line, and a support interposed between the insulating capping line and the contact plugs to limit the height of the air spaces. The width of the support varies or the support is present only intermittently in the first direction. In a method of manufacturing the semiconductor devices, a sacrificial spacer is formed on the side of the stack structure, the spacer is recessed, a support layer is formed in the recess, the support layer is etched to form the support, and then the remainder of the spacer is removed to provide the air spaces.

公开(公告)号：US20150099344A1

公开(公告)日：2015-04-09

申请号：US14283666

申请日：2014-05-21

Applicant: Dae-ik KIM ,  Hyoung-sub KIM ,  Yoo-sang HWANG ,  Nak-jin SON ,  Ji-young KIM

Inventor： Dae-ik KIM ,  Hyoung-sub KIM ,  Yoo-sang HWANG ,  Nak-jin SON ,  Ji-young KIM

IPC: H01L21/762 ,  H01L21/768

CPC classification number: H01L21/76224 ,  H01L21/743 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10891

Abstract: Provided is a method of manufacturing a semiconductor device. The method includes forming a sacrificial film as part of a process of forming a semiconductor device. The sacrificial film has a relatively high etch selectivity with respect to other materials of the semiconductor device so as to reduce loss of etching masks and improve the quality of a components (e.g., buried contacts) of the semiconductor device.

Abstract translation: 提供一种制造半导体器件的方法。 该方法包括形成牺牲膜作为形成半导体器件的工艺的一部分。 牺牲膜相对于半导体器件的其它材料具有相对高的蚀刻选择性，以便减少蚀刻掩模的损耗并提高半导体器件的部件（例如，埋入触点）的质量。

公开(公告)号：US20130288472A1

公开(公告)日：2013-10-31

申请号：US13761376

申请日：2013-02-07

Applicant: Jay-Bok Choi ,  Yoo-Sang Hwang ,  Ah-Young Kim ,  Ye-Ro Lee ,  Gyo-Young Jin ,  Hyeong-sun Hong

Inventor： Jay-Bok Choi ,  Yoo-Sang Hwang ,  Ah-Young Kim ,  Ye-Ro Lee ,  Gyo-Young Jin ,  Hyeong-sun Hong

IPC: H01L29/423

CPC classification number: H01L29/42312 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10888 ,  H01L29/4236 ,  H01L29/66621

Abstract: A method of fabricating a semiconductor device comprises forming a first and a second parallel field regions in a substrate, the parallel field regions are extended in a first direction, forming a first and a second gate capping layer in a first and a second gate trench formed in the substrate respectively, removing the gate capping layers partially so that a first landing pad hole is expanded to overlap the gate capping layers buried in the substrate partially, forming a landing pad material layer in the first space, and forming a bit line contact landing pad by planarizing the landing pad material layer to the level of top surfaces of the capping layers.

Abstract translation: 制造半导体器件的方法包括在衬底中形成第一和第二平行场区域，所述平行场区域沿第一方向延伸，在形成的第一和第二栅极沟槽中形成第一和第二栅极覆盖层 在基板中分别去除栅极覆盖层，使得第一着陆焊盘孔被扩展以部分地覆盖掩埋在衬底中的栅极覆盖层，在第一空间中形成层叠焊盘材料层，并形成位线接触层 通过将着陆垫材料层平坦化到覆盖层的顶表面的水平面。

公开(公告)号：US08420485B2

公开(公告)日：2013-04-16

申请号：US13243174

申请日：2011-09-23

Applicant: Young-seung Cho ,  Dae-ik Kim ,  Yoo-sang Hwang ,  Hyun-woo Chung

Inventor： Young-seung Cho ,  Dae-ik Kim ,  Yoo-sang Hwang ,  Hyun-woo Chung

IPC: H01L21/336

CPC classification number: H01L29/7827 ,  H01L27/0207 ,  H01L27/10876 ,  H01L27/10885 ,  H01L29/66666

Abstract: A semiconductor device and method of manufacturing the same. The method includes: defining a first active area and a second active area on a substrate, the first and second active areas being in a line form, forming a first main trench and a second main trench on the substrate, forming a first sub-trench and a second sub-trench in bottoms of the first and second main trenches, respectively, forming a buried insulation layer filling the first and second sub-trenches, partially exposing the substrate at an area where the first active area crosses with the first sub-trench and an area where the second active area crosses with the second sub-trench and forming the first buried bit line and the second buried bit line on the buried insulation layer, and the first and second buried bit lines being extended in parallel to each other.

Abstract translation: 一种半导体器件及其制造方法。 该方法包括：在衬底上限定第一有源区和第二有源区，第一和第二有源区为线形，在衬底上形成第一主沟槽和第二主沟槽，形成第一子沟槽 以及分别在所述第一和第二主沟槽的底部中的第二子沟槽，形成填充所述第一和第二子沟槽的掩埋绝缘层，在所述第一有源区域与所述第一子沟槽交叉的区域部分地暴露所述衬底， 沟槽和第二有源区域与第二子沟槽交叉的区域，并且在掩埋绝缘层上形成第一掩埋位线和第二掩埋位线，并且第一和第二掩埋位线彼此平行地延伸 。

公开(公告)号：US20120094455A1

公开(公告)日：2012-04-19

申请号：US13243174

申请日：2011-09-23

Applicant: Young-seung CHO ,  Dae-ik Kim ,  Yoo-sang Hwang ,  Hyun-woo Chung

Inventor： Young-seung CHO ,  Dae-ik Kim ,  Yoo-sang Hwang ,  Hyun-woo Chung

IPC: H01L21/336

CPC classification number: H01L29/7827 ,  H01L27/0207 ,  H01L27/10876 ,  H01L27/10885 ,  H01L29/66666

Abstract: A semiconductor device and method of manufacturing the same. The method includes: defining a first active area and a second active area on a substrate, the first and second active areas being in a line form, forming a first main trench and a second main trench on the substrate, forming a first sub-trench and a second sub-trench in bottoms of the first and second main trenches, respectively, forming a buried insulation layer filling the first and second sub-trenches, partially exposing the substrate at an area where the first active area crosses with the first sub-trench and an area where the second active area crosses with the second sub-trench and forming the first buried bit line and the second buried bit line on the buried insulation layer, and the first and second buried bit lines being extended in parallel to each other.

Abstract translation: 一种半导体器件及其制造方法。 该方法包括：在衬底上限定第一有源区和第二有源区，第一和第二有源区为线形，在衬底上形成第一主沟槽和第二主沟槽，形成第一子沟槽 以及分别在所述第一和第二主沟槽的底部中的第二子沟槽，形成填充所述第一和第二子沟槽的掩埋绝缘层，在所述第一有源区域与所述第一子沟槽交叉的区域部分地暴露所述衬底， 沟槽和第二有源区域与第二子沟槽交叉的区域，并且在掩埋绝缘层上形成第一掩埋位线和第二掩埋位线，并且第一和第二掩埋位线彼此平行地延伸 。

公开(公告)号：US20120025300A1

公开(公告)日：2012-02-02

申请号：US13185961

申请日：2011-07-19

Applicant: Hyun-woo Chung ,  Hyeong-sun Hong ,  Yong-chul Oh ,  Yoo-sang Hwang ,  Cheol-ho Baek ,  Kang-uk Kim

Inventor： Hyun-woo Chung ,  Hyeong-sun Hong ,  Yong-chul Oh ,  Yoo-sang Hwang ,  Cheol-ho Baek ,  Kang-uk Kim

IPC: H01L29/78

CPC classification number: H01L27/10876 ,  H01L27/10882 ,  H01L27/10885 ,  H01L27/10891 ,  H01L29/66666 ,  H01L29/7827

Abstract: A semiconductor device including a plurality of buried word lines extending in a first direction and a plurality of buried bit lines extending in a second direction. Upper surfaces of the plurality of buried word lines and the plurality of buried bit lines are lower than an upper surface of a substrate. The distance between two active regions that constitute a pair of first active regions from among a plurality of first active regions included in a first group of active regions is less than the distance between two adjacent active regions having the plurality of buried bit lines therebetween. A method of manufacturing a semiconductor device includes forming a plurality of first trenches in a substrate, forming a plurality of first conductive patterns in the plurality of first trenches in such a manner that a pair of first conductive patterns is disposed in each of the plurality of first trenches, forming a plurality of first buried patterns in the plurality of first trenches to cover the plurality of first conductive patterns, forming a plurality of second trenches by etching the substrate between the plurality of first trenches, and forming a plurality of second buried patterns in the plurality of second trenches.

Abstract translation: 一种半导体器件，包括沿第一方向延伸的多个掩埋字线和沿第二方向延伸的多个掩埋位线。 多个掩埋字线和多个掩埋位线的上表面比衬底的上表面低。 构成第一组有源区域中的多个第一有源区域中的构成一对第一有源区域的两个有源区域之间的距离小于其间具有多个掩埋位线的两个相邻有源区域之间的距离。 一种制造半导体器件的方法包括在衬底中形成多个第一沟槽，在多个第一沟槽中形成多个第一导电图案，使得一对第一导电图案设置在多个第一沟槽中的每一个中 第一沟槽，在所述多个第一沟槽中形成多个第一掩埋图案以覆盖所述多个第一导电图案，通过在所述多个第一沟槽之间蚀刻所述衬底形成多个第二沟槽，以及形成多个第二掩埋图案 在多个第二沟槽中。

公开(公告)号：US07855120B2

公开(公告)日：2010-12-21

申请号：US11780026

申请日：2007-07-19

Applicant: Je-Min Park ,  Yoo-Sang Hwang

Inventor： Je-Min Park ,  Yoo-Sang Hwang

IPC: H01L21/20

CPC classification number: H01L28/20 ,  H01L21/76838 ,  H01L27/0629

Abstract: Methods of forming an integrated circuit device may include forming an insulating layer on an integrated circuit substrate, forming a first conductive layer on the insulating layer, and forming a second conductive layer on the first conductive layer so that the first conductive layer is between the second conductive layer and the insulating layer. Moreover, the first conductive layer may be a layer of a first material, the second conductive layer may be a layer of a second material, and the first and second materials may be different. A hole may be formed in the second conductive layer so that portions of the first conductive layer are exposed through the hole. After forming the hole in the second conductive layer, the first and second conductive layers may be patterned so that portions of the first and second conductive layers surrounding portions of the first conductive layer exposed through the hole are removed while maintaining portions of the first conductive layer previously exposed through the hole.

Abstract translation: 形成集成电路器件的方法可以包括在集成电路衬底上形成绝缘层，在绝缘层上形成第一导电层，在第一导电层上形成第二导电层，使第一导电层位于第二导电层之间 导电层和绝缘层。 此外，第一导电层可以是第一材料的层，第二导电层可以是第二材料的层，并且第一和第二材料可以不同。 可以在第二导电层中形成孔，使得第一导电层的一部分通过该孔露出。 在第二导电层中形成孔之后，可以对第一和第二导电层进行图案化，以使第一导电层和第二导电层的围绕通过孔露出的部分的部分被去除，同时保持第一导电层的部分 以前暴露在洞里。

公开(公告)号：US07749834B2

公开(公告)日：2010-07-06

申请号：US11364635

申请日：2006-02-27

Applicant: Je-Min Park ,  Yoo-Sang Hwang ,  Seok-Soon Song

Inventor： Je-Min Park ,  Yoo-Sang Hwang ,  Seok-Soon Song

IPC: H01L21/8242

CPC classification number: H01L27/10855 ,  H01L27/10817

Abstract: A method includes forming a lower dielectric layer on a semiconductor substrate, forming a bit line landing pad and a storage landing pad that penetrate the lower dielectric layer, covering the lower dielectric layer, the bit line landing pad, and the storage landing pad with an intermediate dielectric layer, forming an upper dielectric layer on the intermediate dielectric layer, partially removing the upper dielectric layer and the intermediate dielectric layer to form a contact opening that exposes the storage landing pad and a portion of the lower dielectric layer, forming a contact spacer on an inner wall of the contact opening, and filling the contact opening with a contact plug, a top surface of the contact plug larger than a surface of the contact plug that is in contact with the storage landing pad, the top surface of the contact plug eccentric in relation to the storage landing pad.

Abstract translation: 一种方法包括在半导体衬底上形成下电介质层，形成位线着陆焊盘和穿透下电介质层的存储着陆焊盘，覆盖下电介质层，位线着陆焊盘和存储着陆焊盘 中间介电层，在中间介电层上形成上电介质层，部分地去除上电介质层和中间电介质层，以形成暴露存储着陆焊盘和下电介质层的一部分的接触开口，形成接触间隔物 在接触开口的内壁上，并用接触塞填充接触开口，接触插塞的顶表面大于接触插塞的与储存着陆垫接触的表面，触头顶表面 相对于存储着陆垫插头偏心。

公开(公告)号：US20090087962A1

公开(公告)日：2009-04-02

申请号：US12325694

申请日：2008-12-01

Applicant: Min-Hee Cho ,  Yoo-Sang Hwang ,  Byung-Hyun Lee

Inventor： Min-Hee Cho ,  Yoo-Sang Hwang ,  Byung-Hyun Lee

IPC: H01L21/02

CPC classification number: H01L27/10894 ,  H01L23/544 ,  H01L27/10814 ,  H01L28/91 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/5446 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a method of fabricating a semiconductor device having an alignment key and a semiconductor device fabricated thereby. The method of fabricating a semiconductor device includes providing a semiconductor substrate having a scribe lane region and a cell region. An etch barrier pattern and a gate pattern are formed on the scribe lane region and the cell region respectively. A first interlayer insulating layer is formed to cover the etch barrier pattern and the gate pattern. A preliminary alignment key pattern and a bit line pattern are formed on the first interlayer insulating layer of the scribe lane region and the cell region respectively. A second interlayer insulating layer is formed to cover the preliminary alignment key pattern and the bit line pattern. The second interlayer insulating layer and the first interlayer insulating layer are patterned to expose the etch barrier pattern, thereby forming an alignment key pattern in the scribe lane region, and concurrently, forming a storage node contact opening in the cell region.

Abstract translation: 在制造具有对准键和由此制造的半导体器件的半导体器件的方法中。 制造半导体器件的方法包括提供具有划线通道区域和单元区域的半导体衬底。 蚀刻阻挡图案和栅极图案分别形成在划线路区域和单元区域上。 形成第一层间绝缘层以覆盖蚀刻阻挡图案和栅极图案。 分别在划线路区域和单元区域的第一层间绝缘层上形成初步对准键图案和位线图案。 形成第二层间绝缘层以覆盖初步对准键图案和位线图案。 将第二层间绝缘层和第一层间绝缘层图案化以暴露蚀刻阻挡图案，从而在划线路区域中形成对准键图案，同时在单元区域中形成存储节点接触开口。

公开(公告)号：US07247906B2

公开(公告)日：2007-07-24

申请号：US11252963

申请日：2005-10-17

Applicant: Je-Min Park ,  Yoo-Sang Hwang

Inventor： Je-Min Park ,  Yoo-Sang Hwang

IPC: H01L29/76 ,  H01L21/8242

CPC classification number: H01L28/91 ,  H01L21/76895 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10855

Abstract: A semiconductor device comprises bit line landing pads and storage landing pads disposed on both sides of the bit line landing pads overlying a substrate. A bit line interlayer insulating layer overlies the bit line and storage landing pads. A plurality of bit line patterns are disposed on the bit line interlayer insulating layer. The bit line patterns each include a bit line and a bit line capping layer pattern. Line insulating layer patterns are placed on a top surface of the bit line interlayer insulating layer. Upper contact holes are placed in a region between the bit line patterns and higher than upper surfaces of the bit lines. Contact hole spacers cover the side walls of the upper contact holes. Lower contact holes are self-aligned with the upper contact holes and extend through the line insulating layer patterns and the bit line interlayer insulating layer, thereby exposing the storage node landing pads.

Abstract translation: 半导体器件包括位线着陆焊盘和设置在覆盖衬底的位线着色焊盘的两侧上的存储着陆焊盘。 位线层间绝缘层覆盖位线和存储着陆焊盘。 多个位线图案设置在位线层间绝缘层上。 位线图案各自包括位线和位线覆盖层图案。 线绝缘层图案被放置在位线层间绝缘层的顶表面上。 上接触孔位于位线图案之间的区域中，高于位线的上表面。 接触孔间隔件覆盖上接触孔的侧壁。 下接触孔与上接触孔自对准并延伸穿过线绝缘层图案和位线层间绝缘层，从而暴露存储节点着陆焊盘。