公开(公告)号：US5390190A

公开(公告)日：1995-02-14

申请号：US890690

申请日：1992-05-29

申请人： Sunil Nanda ,  Rajiv N. Patel

发明人： Sunil Nanda ,  Rajiv N. Patel

IPC分类号： G06F17/50 ,  G01R31/3185 ,  H04B17/00

CPC分类号： G01R31/318552

摘要： In a sequential logic design having two domains, each having opposing clock edge for its flip-flops, an inter-domain latch is provided for establishing a controllable and observable boundary point for the two domains. The inter-domain latch comprises three multiplexors and three latches. The first multiplexor, the first latch, the second multiplexor, the second latch, the third latch and the third multiplexor are coupled serially. Additionally, the output of the first latch is by-passed to the third multiplexor. The latches either open when the clock pulse is low or when the clock pulse is high. The first and third latches are driven by the same clock pulses, and the second latch is driven by an inverted clock pulse. Scan vectors for the first and second domains are scanned in through the first and second multiplexors respectively. The outputs of the first and second domains are observed at the second latch and the third multiplexor respectively.

摘要翻译： 在具有两个域的顺序逻辑设计中，每个域具有用于其触发器的相对的时钟沿，提供了域间锁存器，用于建立两个域的可控和可观察的边界点。 域间锁存器包括三个多路复用器和三个锁存器。 第一多路复用器，第一锁存器，第二多路复用器，第二锁存器，第三锁存器和第三多路复用器被串行耦合。 另外，第一锁存器的输出被旁路到第三多路复用器。 当时钟脉冲为低电平或时钟脉冲为高电平时，锁存器打开。 第一和第三锁存器由相同的时钟脉冲驱动，第二锁存器由反相时钟脉冲驱动。 第一和第二域的扫描向量分别通过第一和第二多路复用器进行扫描。 分别在第二锁存器和第三多路复用器处观察第一和第二域的输出。

公开(公告)号：US4797852A

公开(公告)日：1989-01-10

申请号：US825652

申请日：1986-02-03

申请人： Sunil Nanda

发明人： Sunil Nanda

IPC分类号： G06F12/02 ,  G06F3/00 ,  G06F5/01 ,  G06F7/36 ,  G06F7/76 ,  G06F12/00 ,  G06T3/60 ,  G06F7/00 ,  G11C19/00

CPC分类号： G06F5/015 ,  G06F7/768

摘要： An improved bit shifter to provide data block shifting in a graphics processor. The shifter allows a multiple word, data block shifting to be achieved simultaneously and independently of other graphic functions. The shifter provides character block transfer for rotation of characters of a display. The shifter also provides bit block transfers for moving data from a source location to a destination location.

摘要翻译： 一种改进的位移器，用于在图形处理器中提供数据块移位。 移位器允许同时且独立于其他图形功能实现多个字，数据块移位。 移位器为显示器的字符旋转提供字符块传输。 移位器还提供用于将数据从源位置移动到目标位置的位块传输。

公开(公告)号：US5958038A

公开(公告)日：1999-09-28

申请号：US966904

申请日：1997-11-07

申请人： Nitin Agrawal ,  Sunil Nanda

发明人： Nitin Agrawal ,  Sunil Nanda

IPC分类号： G06F7/00 ,  G06F9/30 ,  G06F9/302 ,  G06F9/345 ,  G06F9/38 ,  G06F15/00

CPC分类号： G06F9/3001 ,  G06F9/3013 ,  G06F9/345 ,  G06F9/3885

摘要： A processor having a modified Harvard architecture having first and second memories, an address register file divided into first and second sets of registers, first and second stream registers, and a general purpose register file for performing data streaming. The first and second sets of registers respectively address the first and second memories which, in turn, load data into the first and second stream registers. An arithmetic logic unit (ALU) accepts the stream registers and general purpose registers as inputs. Stream instructions are encoded such that a single instruction specifies an ALU operation performed on selected ALU inputs and where to store the results of the ALU operation, loads new values into the stream registers, and updates the address registers. A stream instruction has three operand fields respectively specifying two operands for the next ALU operation and a location to store the result of the current ALU operation. The bits in the fields for specifying a stream register and addressing mode are positionally overlapped with the bits for specifying a particular general purpose register. This encoding allows a simple instruction decoding mechanism while enabling parallel memory accesses and address update in a compact instruction.

摘要翻译： 具有经修改的哈佛架构的处理器具有第一和第二存储器，被分成第一和第二组寄存器的地址寄存器文件，第一和第二流寄存器以及用于执行数据流的通用寄存器文件。 第一和第二组寄存器分别对第一和第二存储器进行寻址，其又将数据加载到第一和第二流寄存器中。 算术逻辑单元（ALU）接受流寄存器和通用寄存器作为输入。 流指令被编码，使得单个指令指定对所选ALU输入执行的ALU操作以及在哪里存储ALU操作的结果，将新值加载到流寄存器中，并更新地址寄存器。 流指令具有三个操作数字段，分别指定下一个ALU操作的两个操作数和存储当前ALU操作结果的位置。 用于指定流寄存器和寻址模式的字段中的位与用于指定特定通用寄存器的位位置地重叠。 该编码允许简单的指令解码机制，同时在紧凑指令中实现并行存储器访问和地址更新。

公开(公告)号：US5329627A

公开(公告)日：1994-07-12

申请号：US870356

申请日：1992-04-17

申请人： Sunil Nanda ,  Norman M. Hayes

发明人： Sunil Nanda ,  Norman M. Hayes

IPC分类号： G06F12/10 ,  G06F12/08 ,  G06F12/12

CPC分类号： G06F12/121

摘要： A method and apparatus for selecting an entry to be replaced in a translation lookaside buffer in a computer system. The translation lookaside buffer stores a plurality of entries of virtual-to-physical address translations with each entry having a used bit and a valid bit. The circuit comprises a validity circuit coupled to the valid bit of each entry for determining whether the entry is valid and if not, the validity circuit causes a first signal to be asserted; a use circuit coupled to the used bit of each entry and to the validity circuit for determining whether the entry is used when a control signal is present and if not, the use circuit asserts a second signal to the validity circuit, the asserted second signal causing the first signal to be asserted; a ripple circuit coupled to each entry, its previous entry and its next entry, the ripple circuit receiving the first signal from the validity circuit of each entry and a first FOUND signal from its previous entry, the ripple circuit outputting a second FOUND signal, the ripple circuit causing the second FOUND signal to be asserted when the first signal is asserted and the first FOUND signal is de-asserted, the ripple circuit causing the second FOUND signal to be asserted when the first FOUND signal is asserted, the second FOUND signal being input to the ripple circuit of its next entry, wherein an asserted second FOUND signal for an entry causes the second FOUND signal for its next entry to be asserted, such that an entry with an asserted second FOUND signal propagates the asserted second FOUND signal through its next consecutive entries.

摘要翻译： 一种用于在计算机系统中的翻译后备缓冲器中选择要被替换的条目的方法和装置。 翻译后备缓冲器存储虚拟到物理地址转换的多个条目，每个条目具有使用位和有效位。 电路包括耦合到每个条目的有效位的有效电路，用于确定该条目是否有效，如果不是，有效电路使第一信号被断言; 耦合到每个条目的使用位的使用电路和用于确定在存在控制信号时是否使用条目的有效性电路，如果不是，则使用电路向有效电路断言第二信号，导致所产生的第二信号 要被断言的第一个信号; 纹波电路，其耦合到每个条目，其先前条目和下一条目，纹波电路从每个条目的有效性电路接收第一信号和来自其前一条目的第一FOUND信号，纹波电路输出第二FOUND信号， 当第一个信号被置位并且第一个FOUND信号被断言时，导致第二个FOUND信号产生第二个FOUND信号的纹波电路，当第一个FOUND信号被置位时，引起第二个FOUND信号的纹波电路被断言，第二个FOUND信号是 输入到其下一条目的纹波电路，其中用于条目的断言的第二FOUND信号导致其下一条目的第二FOUND信号被断言，使得具有被断言的第二FOUND信号的条目将被断言的第二FOUND信号传播通过其 下一个连续的条目。

公开(公告)号：US20230001126A1

公开(公告)日：2023-01-05

申请号：US17557752

申请日：2021-12-21

申请人： Sunil Nanda ,  Pankaj Kumar Porwal

发明人： Sunil Nanda ,  Pankaj Kumar Porwal

IPC分类号： A61M16/20 ,  A61M16/00

摘要： Provided is a ventilator that includes a breathing system, a mechanical system coupled to breathing system, and a control system coupled to breathing system and mechanical system. The control system includes pressure sensors, processing circuitry, and memory configured to store a look-up table. The processing circuitry receives a set of values for plurality of parameters, identifies a compression value from a plurality of compression values in the look-up table based on the received set of values. The processing circuitry causes the mechanical system to compress a bag valve of the breathing system in accordance with the identified compression value. The compression of the bag valve causes a gaseous inhalant to flow through the breathing system within a time-interval. The processing circuitry determines an actual volume of the gaseous inhalant and iteratively modifies the compression value of the bag valve to match a desired volume of the gaseous inhalant.

公开(公告)号：US6044448A

公开(公告)日：2000-03-28

申请号：US991392

申请日：1997-12-16

申请人： Nitin Agrawal ,  Sunil Nanda

发明人： Nitin Agrawal ,  Sunil Nanda

IPC分类号： G06F7/00 ,  G06F9/30 ,  G06F9/315 ,  G06F9/38 ,  G06F15/16 ,  G06F15/78 ,  G06F15/80 ,  G06F15/00

CPC分类号： G06F9/30032 ,  G06F15/7867 ,  G06F15/8015 ,  G06F9/30036 ,  G06F9/30101 ,  G06F9/30109 ,  G06F9/3885

摘要： A processor having a sliceable architecture wherein a slice is the minimum configuration of the processor datapath. The processor can instantiate multiple slices and each slice has a separate datapath. The total processor datapath is the sum of the number of slices multiplied by the width of a slice. Accordingly, all general purpose registers in the processor are as wide as the total datapath. A program executing on the processor can determine the maximum number of slices available in a particular processor by reading a register. In addition, a program can select the number of slices it will use by writing to a different register. The processor replicates control signals for each active slice in the processor and supports instructions for transferring data among the slices. Furthermore, the processor supports a set of instructions for fetching and storing data between multiple slices and the memory. The effective addresses of the fetch and store instructions can either be aligned or misaligned with respect to slice boundaries and doubleword boundaries in the memory.

摘要翻译： 具有可切片架构的处理器，其中切片是处理器数据路径的最小配置。 处理器可以实例化多个片段，每个片段具有单独的数据路径。 总处理器数据路径是切片数乘以切片宽度的总和。 因此，处理器中的所有通用寄存器与总数据路径一样宽。 在处理器上执行的程序可以通过读取寄存器来确定特定处理器中可用的最大片数。 此外，程序可以通过写入不同的寄存器来选择要使用的片数。 处理器为处理器中的每个活动切片重复控制信号，并且支持在切片之间传送数据的指令。 此外，处理器支持用于在多个片和存储器之间取出和存储数据的一组指令。 获取和存储指令的有效地址可以相对于存储器中的切片边界和双字边界对准或不对准。

公开(公告)号：US5509130A

公开(公告)日：1996-04-16

申请号：US355804

申请日：1994-12-14

申请人： Richard D. Trauben ,  Sunil Nanda

发明人： Richard D. Trauben ,  Sunil Nanda

IPC分类号： G06F9/38

CPC分类号： G06F9/3804 ,  G06F9/3838 ,  G06F9/3853 ,  G06F9/3867

摘要： In a pipelined processor, an instruction queue and an instruction control unit is provided to group and issue m instructions simultaneously per clock cycle for execution. An integer and a floating point function unit capable of generating n.sub.1 and n.sub.2 integer and floating point results per clock cycle respectively, where n.sub.1 and n.sub.2 are sufficiently large to support m instructions being issued per clock cycle, is also provided to complement the instruction queue and instruction control unit. The pipeline stages are divided into integer and floating point pipeline stages where the early floating point stages overlap with the later integer pipeline stages. The instruction queue stores sequential instructions of a program and target instructions of a branch instruction of the program, fetched from the instruction cache. The instruction control unit decodes the instructions, detects operands cascading from instruction to instruction, group instructions into instruction groups of at most m instructions applying a number of exclusion rules, and issuing the grouped instructions simultaneously to the integer and/or floating point unit for execution. The exclusion rules reflect the resource characteristics and the particular implementation of the pipelined processor. The instruction control unit also tracks the history of the instruction groups and uses the history in conjunction with the exclusion rules in forming the instruction groups.

摘要翻译： 在流水线处理器中，提供指令队列和指令控制单元，用于每个时钟周期同时分组和发出m个指令以执行。 一个整数和一个浮点函数单元，能够分别产生每个时钟周期n1和n2整数和浮点结果，其中n1和n2足够大以支持每个时钟周期发出m个指令，以补充指令队列和 指令控制单元。 流水线阶段分为整数和浮点流水线阶段，其中早期浮点阶段与较后整数流水线阶段重叠。 指令队列存储程序的顺序指令和从指令高速缓存取出的程序的分支指令的目标指令。 指令控制单元对指令进行解码，检测从指令到指令级联的操作数，将指令分组到最多m个指令应用多个排除规则的指令组，同时将分组指令同时发送到整数和/或浮点单元进行执行 。 排除规则反映了流水线处理器的资源特性和特定实现。 指令控制单元还跟踪指令组的历史，并在形成指令组时使用历史与排除规则相结合。

公开(公告)号：US5497480A

公开(公告)日：1996-03-05

申请号：US282170

申请日：1994-07-29

申请人： Norman M. Hayes ,  Pradeep Sindhu ,  Jean-Marc Frailong ,  Sunil Nanda

发明人： Norman M. Hayes ,  Pradeep Sindhu ,  Jean-Marc Frailong ,  Sunil Nanda

IPC分类号： G06F12/08 ,  G06F12/10 ,  G06F13/364 ,  G06F12/12 ,  H04J3/24

CPC分类号： G06F12/1027 ,  G06F12/0831 ,  G06F13/364 ,  G06F2212/682

摘要： A method and apparatus for removing a page table entry from a plurality of translation lookaside buffers ("TLBs") in a multiprocessor computer system. The multiprocessor computer system includes at least two processors coupled to a packet-switched bus. Page table entries are removed from a plurality of TLBs in the multiprocessor computer system by first broadcasting a demap request packet on the packet-switched bus in response to one of the processors requesting that a page table entry be removed from its associated TLB. The demap request packet includes a virtual address and context information specifying this page table entry. Controllers reply to the demap request packet by sending a first reply packet to the controller that sent the original demap request packet to indicate receipt of the demap request packet. If a controller removes the page table entry from its associated TLB, that controller sends a second demap reply packet to indicate that the page table entry has been removed from its associated TLB.

摘要翻译： 一种用于从多处理器计算机系统中的多个翻译后备缓冲器（“TLB”）中移除页表条目的方法和装置。 多处理器计算机系统包括耦合到分组交换总线的至少两个处理器。 通过首先在分组交换总线上广播解映射请求分组来响应于处理器中的一个请求从其相关联的TLB中移除页表项，从多个处理器计算机系统中的多个TLB中移除页表项。 解映射请求分组包括指定该页表项的虚拟地址和上下文信息。 控制器通过向发送原始解映射请求分组的控制器发送第一应答分组来响应解映射请求分组，以指示解映射请求分组的接收。 如果控制器从相关联的TLB中删除页表项，则该控制器发送第二解映射应答分组以指示该页表项已经从其关联的TLB中移除。