-
公开(公告)号：US06822654B1
公开(公告)日：2004-11-23
申请号：US10038700
申请日：2001-12-31
申请人： Sushma Shrikant Trivedi , Joseph P. Bratt , Jack Benkual , Vaughn Todd Arnold , Yutaka Takahashi , Steven Todd Weybrew , Derek Fujio Iwamoto , David Ligon
发明人： Sushma Shrikant Trivedi , Joseph P. Bratt , Jack Benkual , Vaughn Todd Arnold , Yutaka Takahashi , Steven Todd Weybrew , Derek Fujio Iwamoto , David Ligon
IPC分类号： G06F1314
CPC分类号： G06F13/1668
摘要： At least one chip of a chipset in a computer system having at least one host processor and a host memory are described herein. In one aspect of the invention, an exemplary chip includes an interconnect, a memory interface coupled to the interconnect, the memory interface providing access to the host memory and controlling memory refresh and memory access, a host interface coupled to the interconnect, the host interface providing access to the host processor, and a programmable media processor coupled to the interconnect, the media processor accessing the host through the host interface and the media processor accessing the host memory through the memory interface, wherein the media processor processes time based media.
摘要翻译： 本文中描述了具有至少一个主机处理器和主机存储器的计算机系统中的芯片组的至少一个芯片。 在本发明的一个方面中，示例性芯片包括互连，耦合到互连的存储器接口，存储器接口，提供对主机存储器的访问和控制存储器刷新和存储器访问，耦合到互连的主机接口，主机接口 提供对主处理器的访问，以及耦合到互连的可编程媒体处理器，媒体处理器通过主机接口访问主机，并且媒体处理器通过存储器接口访问主机存储器，其中媒体处理器处理基于时间的媒体。
-
公开(公告)号：US07305540B1
公开(公告)日：2007-12-04
申请号：US10038742
申请日：2001-12-31
申请人： Sushma Shrikant Trivedi , Joseph P. Bratt , Jack Benkual , Vaughn Todd Arnold , Derek Fujio Iwamoto
发明人： Sushma Shrikant Trivedi , Joseph P. Bratt , Jack Benkual , Vaughn Todd Arnold , Derek Fujio Iwamoto
CPC分类号： G06F9/3885 , G06F9/30014 , G06F9/30032 , G06F9/30036 , G06F9/3004 , G06F9/30047 , G06F9/30101 , G06F9/3802 , G06F9/382 , G06F9/3853 , G06F9/3879 , G06F15/8053
摘要： Methods and apparatuses for a data processing system are described herein. In one aspect of the invention, an exemplary apparatus includes a chip interconnect, a memory controller for controlling the host memory comprising DRAM memory, the memory controller coupled to the chip interconnect, a scalar processing unit coupled the chip interconnect wherein the scalar processing unit is capable of executing instructions to perform scalar data processing, a vector processing unit coupled the chip interconnect wherein the vector processing unit is capable of executing instructions to perform vector data processing, and an input/output (I/O) interface coupled to the chip interconnect wherein the I/O interface receives/transmits data from/to the scalar and/or vector processing units.
摘要翻译： 本文描述了用于数据处理系统的方法和装置。 在本发明的一个方面中，示例性装置包括芯片互连，用于控制主机存储器的存储器控制器，其包括DRAM存储器，耦合到芯片互连的存储器控制器，耦合芯片互连的标量处理单元，其中标量处理单元 能够执行指令执行标量数据处理的矢量处理单元，耦合芯片互连的矢量处理单元，其中矢量处理单元能够执行执行向量数据处理的指令，以及耦合到芯片互连的输入/输出（I / O） 其中I / O接口从标量和/或向量处理单元接收/发送数据。
-
3.发明授权Method and apparatus for forming and dispatching instruction groups based on priority comparisons 有权基于优先级比较的形成和调度指令组的方法和装置公开(公告)号：US07114058B1
公开(公告)日：2006-09-26
申请号：US10038383
申请日：2001-12-31
申请人： Sushma Shrikant Trivedi , Joseph P. Bratt , Jack Benkual , Ronald Ray Hochsprung , Derek Fujio Iwamoto
发明人： Sushma Shrikant Trivedi , Joseph P. Bratt , Jack Benkual , Ronald Ray Hochsprung , Derek Fujio Iwamoto
IPC分类号： G06F9/30
CPC分类号： G06F9/3853 , G06F9/30014 , G06F9/30021 , G06F9/30032 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/3836 , G06F9/3855 , G06F9/3857 , G06F9/3867 , G06F9/3879 , G06F9/3885
摘要： Methods and apparatuses for dispatching instructions executed by at least one functional unit of a data processor, each one of the instructions having a corresponding priority number, in a data processing system having at least one host processor with host processor cache and host memory are described herein. In one aspect of the invention, an exemplary method includes receiving a next instruction from an instruction stream, examining a current instruction group to determine if the current instruction group is completed, adding the next instruction to the current instruction group if the current instruction group is not completed, and dispatching the current instruction group if the current instruction group is completed.
摘要翻译： 本文描述了在具有至少一个具有主处理器高速缓存和主机存储器的主机处理器的数据处理系统中调度由数据处理器的至少一个功能单元执行的指令的方法和装置，每个指令具有相应的优先级号码 。 在本发明的一个方面，一种示例性方法包括从指令流接收下一条指令，检查当前指令组以确定当前指令组是否完成，如果当前指令组是 未完成，如果当前指令组完成，则调度当前指令组。
-
公开(公告)号：US07558947B1
公开(公告)日：2009-07-07
申请号：US10038431
申请日：2001-12-31
IPC分类号： G06F7/38
CPC分类号： G06F7/544 , G06F2207/5442
摘要： Methods and apparatuses for computing an absolute difference of two vectors of numbers. In one aspect of the invention, a method for execution by a microprocessor in response to receiving a single instruction includes: receiving a first plurality of numbers and a second plurality of numbers; and generating simultaneously a third plurality of numbers, each of which is an absolute difference between a number in the first plurality of numbers and a number in the second plurality of numbers. The above operations are performed in response to the microprocessor receiving the single instruction.
摘要翻译： 用于计算两个数字向量的绝对差的方法和装置。 在本发明的一个方面中，微处理器响应于接收单个指令而执行的方法包括：接收第一多个数字和第二多个数字; 并且同时产生第三多个数字，每个数字是第一多个数字中的数字和第二个多个数字中的数字之间的绝对差。 响应于微处理器接收到单个指令执行上述操作。
-
5.发明授权Method for variable length decoding using multiple configurable look-up tables 有权使用多个可配置查找表进行可变长度解码的方法公开(公告)号：US07681013B1
公开(公告)日：2010-03-16
申请号：US10038473
申请日：2001-12-31
IPC分类号： G06F9/30
CPC分类号： G06F9/30032 , G06F9/30014 , G06F9/30047 , G06F9/30101 , G06F9/30109 , G06F9/3013 , G06F9/30141 , G06F9/3802 , G06F9/3836 , G06F9/3853 , G06F9/3877 , G06F9/3879 , G06F9/3885 , G06F9/3895
摘要： Methods and apparatuses for variable length decoding using multiple look-up tables simultaneously. In one aspect of the invention, a method for execution by a microprocessor in response to receiving a single instruction includes: receiving a string of bits; generating a plurality of indices using a plurality of segments of bits in the string of bits; looking up simultaneously a plurality of entries from a plurality of look-up tables using the plurality of indices; and combining the plurality of entries into a first result. The above operations are performed in response to the microprocessor receiving the single instruction.
摘要翻译： 同时使用多个查找表进行可变长度解码的方法和装置。 在本发明的一个方面，微处理器响应于接收单个指令而执行的方法包括：接收一串比特; 使用所述比特串中的多个比特段来生成多个索引; 使用多个索引从多个查找表中同时查找多个条目; 以及将所述多个条目组合成第一结果。 响应于微处理器接收到单个指令执行上述操作。
-
公开(公告)号：US07467287B1
公开(公告)日：2008-12-16
申请号：US10038478
申请日：2001-12-31
IPC分类号： G06F7/00
CPC分类号： G06F9/383 , G06F9/30014 , G06F9/30021 , G06F9/30032 , G06F9/30036 , G06F9/3004 , G06F9/345 , G06F9/3836 , G06F9/3853 , G06F9/3855 , G06F9/3885
摘要： Methods and apparatuses for performing vector table look-up using multiple look-up tables. In one aspect of the invention, a method for execution by a microprocessor in response to receiving a single instruction includes: receiving a plurality of numbers; partitioning look-up memory into a plurality of look-up tables; looking up simultaneously a plurality of elements from the plurality of look-up tables. Each of the plurality of elements is in one of the plurality of look-up tables and is pointed to by one of the plurality of numbers. The above operations are performed in response to the microprocessor receiving the single instruction.
摘要翻译： 使用多个查找表执行向量表查找的方法和装置。 在本发明的一个方面，一种微处理器响应于接收单个指令而执行的方法包括：接收多个数字; 将查找存储器分割成多个查找表; 同时从多个查找表中同时查找多个元素。 多个元素中的每一个在多个查找表中的一个中，并且由多个数字之一指向。 响应于微处理器接收到单个指令执行上述操作。
-
公开(公告)号：US07055018B1
公开(公告)日：2006-05-30
申请号：US10038351
申请日：2001-12-31
IPC分类号： G06F15/00
CPC分类号： G06F9/3004 , G06F9/30014 , G06F9/30018 , G06F9/30025 , G06F9/30101 , G06F9/3853 , G06F9/3879 , G06F9/3885 , G06F9/3891 , G06F15/8076 , H04N19/423 , H04N19/436 , H04N19/44
摘要： Methods and apparatuses for performing simultaneous table look-up using multiple look-up tables. In one aspect of the invention, an execution unit in a microprocessor includes: look-up memory and a first circuit coupled to the look-up memory. In response to the microprocessor receiving a first instruction, the first circuit partitions the look-up memory into a first plurality of look-up tables. In response to the microprocessor receiving a second instruction, the first circuit partitions the look-up memory into a second plurality of look-up tables; and the second plurality of look-up tables simultaneously look up a plurality of entries.
摘要翻译： 使用多个查找表执行同时表查找的方法和装置。 在本发明的一个方面，微处理器中的执行单元包括：查找存储器和耦合到查找存储器的第一电路。 响应于微处理器接收到第一指令，第一电路将查找存储器分割成第一多个查找表。 响应于微处理器接收第二指令，第一电路将查找存储器划分成第二多个查找表; 并且第二多个查找表同时查找多个条目。
-
公开(公告)号：US06697076B1
公开(公告)日：2004-02-24
申请号：US10038456
申请日：2001-12-31
IPC分类号： G06F1210
CPC分类号： G06F12/1027 , G06F12/0815 , G06F12/1009 , G06F12/1081
摘要： Methods and apparatuses for mapping a logical address to a physical address, in a data processing system having at least one host processor with host processor cache and host memory. In one aspect of the invention, an exemplary method includes translating a memory access request from logical addresses to physical addresses through a memory mapping mechanism, determining whether the physical address is configured for cache coherent access, if so, transmitting the request to cache coherent interface, and otherwise, transmitting the request to cache non-coherent interface. Other methods and apparatuses are also described.
摘要翻译： 在具有至少一个具有主处理器高速缓存和主机存储器的主机处理器的数据处理系统中，将逻辑地址映射到物理地址的方法和装置。 在本发明的一个方面，一种示例性方法包括通过存储器映射机制将存储器访问请求从逻辑地址转换为物理地址，确定物理地址是否被配置用于高速缓存一致性访问，如果是，将请求发送到高速缓存相干接口 ，否则，将请求发送到高速缓存非相干接口。 还描述了其它方法和装置。
-
公开(公告)号：US07015921B1
公开(公告)日：2006-03-21
申请号：US10038905
申请日：2001-12-31
IPC分类号： G09G5/36
CPC分类号： G06F12/0831 , G06F13/1668
摘要： An apparatus, in a data processing system having at least one host processor with host processor cache and host memory, includes a chip interconnect, a cache coherent interface coupled to the chip interconnect wherein the cache coherent interface provides cache coherent access, a cache non-coherent interface coupled to the chip interconnect wherein the cache non-coherent interface provides cache non-coherent access to the host memory, and a compute engine coupled to the chip interconnect and coupled to the cache coherent interface and coupled to cache non-coherent interface wherein the compute engine issues a memory access request. Other methods and apparatuses are also described.
摘要翻译： 具有至少一个具有主处理器高速缓存和主机存储器的主机处理器的数据处理系统中的装置包括芯片互连，耦合到芯片互连的高速缓存相干接口，其中高速缓存相干接口提供高速缓存一致性访问， 耦合到芯片互连的相干接口，其中高速缓存非相干接口提供对主机存储器的高速缓存非相干访问，以及耦合到芯片互连并耦合到高速缓存相干接口并耦合到高速缓存非相干接口的计算引擎，其中 计算引擎发出内存访问请求。 还描述了其它方法和装置。
-
公开(公告)号：US06693643B1
公开(公告)日：2004-02-17
申请号：US10038301
申请日：2001-12-31
IPC分类号： G06F1500
CPC分类号： H04N9/64 , H04N9/69 , H04N11/042
摘要： Methods and apparatuses for converting color components in one space to those in another space. In one aspect of the invention, a method for vector conversion including: loading a first vector of components into a vector register; generating a first vector of indices in a vector register, each index of the first vector of indices being one of the first vector of components, at least one component in the first vector of components being replicated as a plurality of duplicated indices in the first vector of indices; looking up simultaneously a first vector of data items from a plurality of look up tables using the first vector of indices; and summing up at least one subset of the first vector of data items into at least one component of a second vector of components.
摘要翻译： 将一个空间中的颜色分量转换成另一个空间中的颜色分量的方法和装置。 在本发明的一个方面，一种用于向量转换的方法，包括：将第一向量的分量加载到向量寄存器中; 在向量寄存器中产生索引的第一向量，第一索引向量的每个索引是组件的第一向量之一，组件的第一向量中的至少一个组件被复制为第一向量中的多个重复索引 的指标; 使用第一索引向量同时查找来自多个查找表的数据项的第一向量; 以及将所述第一数据项向量的至少一个子集合到所述第二组分向量的至少一个分量中。
-
-
-
-
-
-
-
-
-
搜索结果
11 条记录 (耗时 0.045 秒)