公开(公告)号：US5267198A

公开(公告)日：1993-11-30

申请号：US953747

申请日：1992-09-29

申请人： Susumu Hatano ,  Kanji Oishi ,  Takashi Kikuchi ,  Yasuhiko Saigou ,  Hiroshi Fukuta ,  Kunio Uchiyama ,  Hirokazu Aoki ,  Osamu Nishii

发明人： Susumu Hatano ,  Kanji Oishi ,  Takashi Kikuchi ,  Yasuhiko Saigou ,  Hiroshi Fukuta ,  Kunio Uchiyama ,  Hirokazu Aoki ,  Osamu Nishii

IPC分类号： G11C11/419 ,  G06F12/08 ,  G11C7/06 ,  G11C11/40 ,  G11C11/41 ,  H01L27/10

CPC分类号： G11C7/065

摘要： A static memory cell is connected with word lines and data lines. First and second switches are connected in series between a data line and on output circuit. A sense amplifier has an input/output terminal connected to a common connection point of the said first and second switches. The first switch is turned off in synchronism with commencing operation of the sense amplifier such that the parasitic capacitance of the data line as viewed from the sense amplifier decreases. The second switching means is turned on a predetermined time later in order to transmit the output signal of the sense amplifier to the output circuit.

摘要翻译： 静态存储单元与字线和数据线连接。 第一和第二开关串联连接在数据线和输出电路之间。 读出放大器具有连接到所述第一和第二开关的公共连接点的输入/输出端子。 第一开关与读出放大器的开始操作同步关闭，使得从读出放大器观察的数据线的寄生电容减小。 为了将读出放大器的输出信号发送到输出电路，第二开关装置在预定的时间之后被接通。

公开(公告)号：US5193075A

公开(公告)日：1993-03-09

申请号：US490745

申请日：1990-03-08

申请人： Susumu Hatano ,  Kanji Oishi ,  Takashi Kikuchi ,  Yasuhiko Saigou ,  Hiroshi Fukuta ,  Kunio Uchiyama ,  Hirokazu Aoki ,  Osamu Nishii

发明人： Susumu Hatano ,  Kanji Oishi ,  Takashi Kikuchi ,  Yasuhiko Saigou ,  Hiroshi Fukuta ,  Kunio Uchiyama ,  Hirokazu Aoki ,  Osamu Nishii

IPC分类号： G11C11/419 ,  G06F12/08 ,  G11C7/06 ,  G11C11/40 ,  G11C11/41 ,  H01L27/10

CPC分类号： G11C7/065

摘要： A static memory cell is connected with word lines and data lines. First and second switches are connected in series between a data line and an output circuit. A sense amplifier has an input/output terminal connected to a common connection point of the said first and second switches. The first switch is turned off in synchronism with commencing operation of the sense amplifier such that the parasitic capacitance of the data line as viewed from the sense amplifier decreases. The second switching means is turned on a predetermined time later in order to transmit the output signal of the sense amplifier to the output circuit.

摘要翻译： 静态存储单元与字线和数据线连接。 第一和第二开关串联连接在数据线和输出电路之间。 读出放大器具有连接到所述第一和第二开关的公共连接点的输入/输出端子。 第一开关与读出放大器的开始操作同步关闭，使得从读出放大器观察的数据线的寄生电容减小。 为了将读出放大器的输出信号发送到输出电路，第二开关装置在预定的时间之后被接通。

公开(公告)号：US5202969A

公开(公告)日：1993-04-13

申请号：US871906

申请日：1992-04-21

申请人： Katsuyuki Sato ,  Tadahiko Nishimukai ,  Kunio Uchiyama ,  Hirokazu Aoki ,  Susumu Hatano ,  Kanji Oishi ,  Hiroshi Fukuta ,  Takashi Kikuchi ,  Yasuhiko Saigou

发明人： Katsuyuki Sato ,  Tadahiko Nishimukai ,  Kunio Uchiyama ,  Hirokazu Aoki ,  Susumu Hatano ,  Kanji Oishi ,  Hiroshi Fukuta ,  Takashi Kikuchi ,  Yasuhiko Saigou

IPC分类号： G06F12/08 ,  G11C11/4096

CPC分类号： G06F12/0804 ,  G11C11/4096

摘要： In a cache memory setup, a buffer register is provided to accommodate the data read from a data memory. Between the buffer register and the data memory is connected a selector. This selector selectively transfers to the buffer register part of the data read from the data memory. The remaining part of the data is replaced with appropriate data for transfer to the buffer register. This arrangement provides the cache memory with a partial-write function.

摘要翻译： 在缓存存储器设置中，提供缓冲寄存器以容纳从数据存储器读取的数据。 在缓冲寄存器和数据存储器之间连接一个选择器。 该选择器选择性地将从数据存储器读取的数据传送到缓冲寄存器部分。 数据的剩余部分被替换为适当的数据以传送到缓冲寄存器。 这种布置为高速缓冲存储器提供部分写入功能。

公开(公告)号：US5140681A

公开(公告)日：1992-08-18

申请号：US355680

申请日：1989-05-23

申请人： Kunio Uchiyama ,  Hirokazu Aoki ,  Susumu Hatano ,  Kanji Oishi ,  Takashi Kikuchi ,  Hiroshi Fukuta ,  Yasuhiko Saigou

发明人： Kunio Uchiyama ,  Hirokazu Aoki ,  Susumu Hatano ,  Kanji Oishi ,  Takashi Kikuchi ,  Hiroshi Fukuta ,  Yasuhiko Saigou

IPC分类号： G06F12/08 ,  G06F15/16

CPC分类号： G06F12/0815 ,  G06F2212/621

摘要： A main memory is subdivided into a shared region to undergo a write access from a plurality of processors and an input/output device and a plurality of private regions to undergo a write access only from the associated processor. Each of the cache devices includes a region discriminating circuit for determining whether an address generated from the processor is to be employed for an access to the shared region or to the private regions. If the access is to be conducted to the shared region, the cache devices operate according to the write-through method. On the other hand, if the access is to be conducted to the private region, the cache devices operate according to the copy-back method. When the processor or the input/output device rewrites data in the shared region of the main memory, the stored data of the shared region in the cache device of the processor is invalidated.

公开(公告)号：US5146573A

公开(公告)日：1992-09-08

申请号：US426781

申请日：1989-10-25

申请人： Katsuyuki Sato ,  Tadahiko Nishimukai ,  Kunio Uchiyama ,  Hirokazu Aoki ,  Susumu Hatano ,  Kanji Oishi ,  Hiroshi Fukuta ,  Takashi Kikuchi ,  Yasuhiko Saigou

发明人： Katsuyuki Sato ,  Tadahiko Nishimukai ,  Kunio Uchiyama ,  Hirokazu Aoki ,  Susumu Hatano ,  Kanji Oishi ,  Hiroshi Fukuta ,  Takashi Kikuchi ,  Yasuhiko Saigou

IPC分类号： G06F12/08 ,  G11C11/4096

CPC分类号： G11C11/4096 ,  G06F12/0804

摘要： In a cache memory setup, a buffer register is provided to accommodate the data read from a data memory. Between the buffer register and the data memory is connected a selector. This selector selectively transfers to the buffer register part of the data read from the data memory. The remaining part of the data is replaced with appropriate data for transfer to the buffer register. This arrangement provides the cache memory with a partial-write function.

摘要翻译： 在缓存存储器设置中，提供缓冲寄存器以容纳从数据存储器读取的数据。 在缓冲寄存器和数据存储器之间连接一个选择器。 该选择器选择性地将从数据存储器读取的数据传送到缓冲寄存器部分。 数据的剩余部分被替换为适当的数据以传送到缓冲寄存器。 这种布置为高速缓冲存储器提供部分写入功能。

公开(公告)号：US5287484A

公开(公告)日：1994-02-15

申请号：US976645

申请日：1992-11-13

申请人： Osamu Nishii ,  Kunio Uchiyama ,  Hirokazu Aoki ,  Takashi Kikuchi ,  Yasuhiko Saigou

发明人： Osamu Nishii ,  Kunio Uchiyama ,  Hirokazu Aoki ,  Takashi Kikuchi ,  Yasuhiko Saigou

IPC分类号： G06F12/08

CPC分类号： G06F12/0811 ,  G06F12/0897

摘要： A non-shared system with respect to an outside and an inside cache in a multi-processor system has multi-layer hierarchical cache. An invalidation address on a main memory address bus 31 in company with the rewriting of a main memory 30 is transmitted via a first and a second path 35, 36 to inside caches 11,21 so as to invalidate these inside caches 11, 21. The invalidation address is transmitted to the outside caches 12, 22 via the bidirectional connections between the main memory address bus 31 and outside caches 12, 22 so as to invalidate these outside caches 12, 22. It is extremely improbable for the address of access for writing to the transmitted to the main memory address bus 31 because the outside caches 12, 22 are operated in either copy back or write once system. As a result, even though the invalidation address is transmitted to the outside caches 12, 22 via the bidirectional connections between the main memory address bus 31 and the outside caches 12, 22, it is extremely improbably for the address of access for writing to conflict with a signal on the bidirectional connection.

摘要翻译： 关于多处理器系统中的外部和内部高速缓存的非共享系统具有多层分层高速缓存。 主存储器地址总线31上的与主存储器30的重写有关的无效地址经由第一和第二路径35,36被发送到高速缓存11,21内部，以使这些内部缓存11,21无效。 无效地址通过主存储器地址总线31和外部高速缓存12,22之间的双向连接被发送到外部高速缓存12,22，以使这些外部高速缓存12,22成为无效。对于写入访问地址是非常不可能的 由于外部高速缓存12,22以一个或多个拷贝的一次系统操作，所以传送到主存储器地址总线31。 结果，即使无效地址经由主存储器地址总线31和外部高速缓存12,22之间的双向连接被发送到外部高速缓存12,22，对于写入冲突的访问地址极其不可能 在双向连接上有一个信号。