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    Multiprocessor cache system having three states for generating invalidating signals upon write accesses
    6.
    发明授权
    Multiprocessor cache system having three states for generating invalidating signals upon write accesses 失效
    具有三种状态的多处理器缓存系统，用于在写访问时产生无效信号

    公开(公告)号：US5283886A

    公开(公告)日：1994-02-01

    申请号：US950746

    申请日：1992-09-24

    申请人： Osamu Nishii ,  Kunio Uchiyama ,  Hirokazu Aoki ,  Kanji Oishi ,  Jun Kitano ,  Susumu Hatano

    发明人： Osamu Nishii ,  Kunio Uchiyama ,  Hirokazu Aoki ,  Kanji Oishi ,  Jun Kitano ,  Susumu Hatano

    IPC分类号： G06F12/08 ,  G06F12/12

    CPC分类号： G06F12/0833

    摘要： Herein disclosed is a multiprocessor system which comprises first and second processors (1001 and 1002), first and second cache memories (100:#1 and #2), an address bus (123), a data bus (126), an invalidating signal line (PURGE:131) and a main memory (1004). The first and second cache memories are operated by the copy-back method. The state of the data of the first cache (100:#1) exists in one state selected from a group consisting of an invalid first state, a valid and non-updated second state and a valid and updated third state. The second cache (100:#2) is constructed like the first cache. When the write access of the first processor hits the first cache, the state of the data of the first cache is shifted from the second state to the third state, and the first cache outputs the address of the write hit and the invalidating signal to the address bus and the invalidating signal line, respectively. When the write access from the first processor misses the first cache, a data of one block is block-transferred from the main memory to the first cache, and the invalidating signal is outputted. After this, the first cache executes the write of the data in the transfer block. In case the first and second caches hold the data in the third state relating to the pertinent address when an address of an access request is fed to the address bus (123), the pertinent cache writes back the pertinent data in the main memory.

    摘要翻译： 这里公开了一种多处理器系统，其包括第一和第二处理器（1001和1002），第一和第二高速缓冲存储器（100：＃1和＃2），地址总线（123），数据总线（126），无效信号 线（PURGE：131）和主存储器（1004）。 第一和第二高速缓存存储器通过复制方法操作。 第一高速缓存（100：＃1）的数据的状态存在于从由无效的第一状态，有效和未更新的第二状态以及有效和更新的第三状态组成的组中选择的一个状态中。 第二个缓存（100：＃2）被构造成像第一个缓存。 当第一处理器的写入访问第一高速缓存时，第一高速缓存的数据的状态从第二状态转移到第三状态，并且第一高速缓存将写入命中的地址和无效信号输出到 地址总线和无效信号线。 当来自第一处理器的写访问错过第一高速缓存时，一个块的数据被从主存储器块传输到第一高速缓存，并且输出无效信号。 之后，第一个缓存执行传输块中数据的写入。 在第一和第二高速缓冲存储器将存取请求地址与相关地址相关的第三状态的数据保存到地址总线（123）的情况下，相关高速缓冲存储器将相关数据写回到主存储器中。

    Semiconductor memory device having a double branching bidirectional buffer
    8.
    发明授权
    Semiconductor memory device having a double branching bidirectional buffer 有权
    具有双分支双向缓冲器的半导体存储器件

    公开(公告)号：US08054699B2

    公开(公告)日：2011-11-08

    申请号：US12289349

    申请日：2008-10-27

    申请人： Susumu Takahashi ,  Kanji Oishi

    发明人： Susumu Takahashi ,  Kanji Oishi

    IPC分类号： G11C7/10

    CPC分类号： G11C7/1048 ,  G06F13/1673 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1078 ,  G11C7/1084

    摘要： A semiconductor memory device includes a memory cell array divided into a plurality of areas, a common data bus connected to an input/output circuit, a plurality of individual data buses connected to different areas of the memory cell array through different paths respectively, and a bidirectional buffer connected to the common data bus and the individual data buses. In the semiconductor memory device, the bidirectional buffers transmit data bidirectionally between the common data bus and a selected one of the individual data buses.

    摘要翻译： 半导体存储器件包括被划分为多个区域的存储单元阵列，连接到输入/输出电路的公共数据总线，分别通过不同路径连接到存储单元阵列的不同区域的多个独立数据总线，以及 连接到公共数据总线和各个数据总线的双向缓冲器。 在半导体存储器件中，双向缓冲器在公共数据总线和所选择的单个数据总线之间双向传输数据。

    Semiconductor memory
    9.
    发明授权
    Semiconductor memory 有权
    半导体存储器

    公开(公告)号：US07542359B2

    公开(公告)日：2009-06-02

    申请号：US11875390

    申请日：2007-10-19

    申请人： Tomoyuki Shibata ,  Kanji Oishi

    发明人： Tomoyuki Shibata ,  Kanji Oishi

    IPC分类号： G11C29/00 ,  G11C17/18 ,  G11C8/00

    CPC分类号： G11C17/165 ,  G11C29/808 ,  G11C29/846

    摘要： In a semiconductor memory having a plurality of memory banks that can be independently accessed, remedying bit registers that are substituted for defective memory cells are respectively provided for memory banks in a one-to-one relationship. Also, means for sharing the plurality of remedying bit registers in each memory bank is arranged.

    摘要翻译： 在具有可以被独立访问的多个存储体的半导体存储器中，分别以一对一的关系为存储体提供用于代替缺陷存储单元的补偿位寄存器。 此外，布置了用于共享每个存储体中的多个补救位寄存器的装置。

    Duty detection circuit
    10.
    发明授权
    Duty detection circuit 失效
    占空比检测电路

    公开(公告)号：US07411435B2

    公开(公告)日：2008-08-12

    申请号：US11346416

    申请日：2006-02-03

    申请人： Atsuko Monma ,  Kanji Oishi

    发明人： Atsuko Monma ,  Kanji Oishi

    IPC分类号： H03K3/017 ,  H03K5/04 ,  H03K7/08

    CPC分类号： H03K5/1565

    摘要： A duty detection circuit includes an integration circuit for receiving an RCLK signal and an FCLK signal that are internal clock signals generated by a DLL circuit, and generating voltage levels in accordance with the duty ratio of these internal clock signals; an amplifier for amplifying the output of the integration circuit; a latch circuit for latching the output of the amplifier; a control circuit for controlling the operation timings of each component; a bias circuit for feeding a BIAS signal to the integration circuit; and a frequency monitor circuit unit for monitoring the frequency of the clock signal. The frequency monitor circuit unit is a circuit component used when the power source is turned on, during resetting, and when other initial settings are performed, and detects the actual frequency of the clock signal and adjusts the amount of charging or discharging of the capacitors C1 through C4 in the integration circuit according to this actual frequency.

    摘要翻译： 占空比检测电路包括用于接收由DLL电路产生的内部时钟信号的RCLK信号和FCLK信号的积分电路，并且根据这些内部时钟信号的占空比产生电压电平; 用于放大积分电路的输出的放大器; 用于锁存放大器的输出的锁存电路; 用于控制每个部件的操作定时的控制电路; 用于将BIAS信号馈送到积分电路的偏置电路; 以及用于监视时钟信号的频率的频率监视电路单元。 频率监视电路单元是当电源接通，复位期间和执行其它初始设置时使用的电路部件，并且检测时钟信号的实际频率并调节电容器C的充电或放电量 1到C 4在积分电路中根据实际频率。