公开(公告)号：US5267198A

公开(公告)日：1993-11-30

申请号：US953747

申请日：1992-09-29

申请人： Susumu Hatano ,  Kanji Oishi ,  Takashi Kikuchi ,  Yasuhiko Saigou ,  Hiroshi Fukuta ,  Kunio Uchiyama ,  Hirokazu Aoki ,  Osamu Nishii

发明人： Susumu Hatano ,  Kanji Oishi ,  Takashi Kikuchi ,  Yasuhiko Saigou ,  Hiroshi Fukuta ,  Kunio Uchiyama ,  Hirokazu Aoki ,  Osamu Nishii

IPC分类号： G11C11/419 ,  G06F12/08 ,  G11C7/06 ,  G11C11/40 ,  G11C11/41 ,  H01L27/10

CPC分类号： G11C7/065

摘要： A static memory cell is connected with word lines and data lines. First and second switches are connected in series between a data line and on output circuit. A sense amplifier has an input/output terminal connected to a common connection point of the said first and second switches. The first switch is turned off in synchronism with commencing operation of the sense amplifier such that the parasitic capacitance of the data line as viewed from the sense amplifier decreases. The second switching means is turned on a predetermined time later in order to transmit the output signal of the sense amplifier to the output circuit.

摘要翻译： 静态存储单元与字线和数据线连接。 第一和第二开关串联连接在数据线和输出电路之间。 读出放大器具有连接到所述第一和第二开关的公共连接点的输入/输出端子。 第一开关与读出放大器的开始操作同步关闭，使得从读出放大器观察的数据线的寄生电容减小。 为了将读出放大器的输出信号发送到输出电路，第二开关装置在预定的时间之后被接通。

公开(公告)号：US5193075A

公开(公告)日：1993-03-09

申请号：US490745

申请日：1990-03-08

申请人： Susumu Hatano ,  Kanji Oishi ,  Takashi Kikuchi ,  Yasuhiko Saigou ,  Hiroshi Fukuta ,  Kunio Uchiyama ,  Hirokazu Aoki ,  Osamu Nishii

发明人： Susumu Hatano ,  Kanji Oishi ,  Takashi Kikuchi ,  Yasuhiko Saigou ,  Hiroshi Fukuta ,  Kunio Uchiyama ,  Hirokazu Aoki ,  Osamu Nishii

IPC分类号： G11C11/419 ,  G06F12/08 ,  G11C7/06 ,  G11C11/40 ,  G11C11/41 ,  H01L27/10

CPC分类号： G11C7/065

摘要： A static memory cell is connected with word lines and data lines. First and second switches are connected in series between a data line and an output circuit. A sense amplifier has an input/output terminal connected to a common connection point of the said first and second switches. The first switch is turned off in synchronism with commencing operation of the sense amplifier such that the parasitic capacitance of the data line as viewed from the sense amplifier decreases. The second switching means is turned on a predetermined time later in order to transmit the output signal of the sense amplifier to the output circuit.

摘要翻译： 静态存储单元与字线和数据线连接。 第一和第二开关串联连接在数据线和输出电路之间。 读出放大器具有连接到所述第一和第二开关的公共连接点的输入/输出端子。 第一开关与读出放大器的开始操作同步关闭，使得从读出放大器观察的数据线的寄生电容减小。 为了将读出放大器的输出信号发送到输出电路，第二开关装置在预定的时间之后被接通。

公开(公告)号：US5202969A

公开(公告)日：1993-04-13

申请号：US871906

申请日：1992-04-21

申请人： Katsuyuki Sato ,  Tadahiko Nishimukai ,  Kunio Uchiyama ,  Hirokazu Aoki ,  Susumu Hatano ,  Kanji Oishi ,  Hiroshi Fukuta ,  Takashi Kikuchi ,  Yasuhiko Saigou

发明人： Katsuyuki Sato ,  Tadahiko Nishimukai ,  Kunio Uchiyama ,  Hirokazu Aoki ,  Susumu Hatano ,  Kanji Oishi ,  Hiroshi Fukuta ,  Takashi Kikuchi ,  Yasuhiko Saigou

IPC分类号： G06F12/08 ,  G11C11/4096

CPC分类号： G06F12/0804 ,  G11C11/4096

摘要： In a cache memory setup, a buffer register is provided to accommodate the data read from a data memory. Between the buffer register and the data memory is connected a selector. This selector selectively transfers to the buffer register part of the data read from the data memory. The remaining part of the data is replaced with appropriate data for transfer to the buffer register. This arrangement provides the cache memory with a partial-write function.

摘要翻译： 在缓存存储器设置中，提供缓冲寄存器以容纳从数据存储器读取的数据。 在缓冲寄存器和数据存储器之间连接一个选择器。 该选择器选择性地将从数据存储器读取的数据传送到缓冲寄存器部分。 数据的剩余部分被替换为适当的数据以传送到缓冲寄存器。 这种布置为高速缓冲存储器提供部分写入功能。

公开(公告)号：US5140681A

公开(公告)日：1992-08-18

申请号：US355680

申请日：1989-05-23

申请人： Kunio Uchiyama ,  Hirokazu Aoki ,  Susumu Hatano ,  Kanji Oishi ,  Takashi Kikuchi ,  Hiroshi Fukuta ,  Yasuhiko Saigou

发明人： Kunio Uchiyama ,  Hirokazu Aoki ,  Susumu Hatano ,  Kanji Oishi ,  Takashi Kikuchi ,  Hiroshi Fukuta ,  Yasuhiko Saigou

IPC分类号： G06F12/08 ,  G06F15/16

CPC分类号： G06F12/0815 ,  G06F2212/621

摘要： A main memory is subdivided into a shared region to undergo a write access from a plurality of processors and an input/output device and a plurality of private regions to undergo a write access only from the associated processor. Each of the cache devices includes a region discriminating circuit for determining whether an address generated from the processor is to be employed for an access to the shared region or to the private regions. If the access is to be conducted to the shared region, the cache devices operate according to the write-through method. On the other hand, if the access is to be conducted to the private region, the cache devices operate according to the copy-back method. When the processor or the input/output device rewrites data in the shared region of the main memory, the stored data of the shared region in the cache device of the processor is invalidated.

公开(公告)号：US5146573A

公开(公告)日：1992-09-08

申请号：US426781

申请日：1989-10-25

申请人： Katsuyuki Sato ,  Tadahiko Nishimukai ,  Kunio Uchiyama ,  Hirokazu Aoki ,  Susumu Hatano ,  Kanji Oishi ,  Hiroshi Fukuta ,  Takashi Kikuchi ,  Yasuhiko Saigou

发明人： Katsuyuki Sato ,  Tadahiko Nishimukai ,  Kunio Uchiyama ,  Hirokazu Aoki ,  Susumu Hatano ,  Kanji Oishi ,  Hiroshi Fukuta ,  Takashi Kikuchi ,  Yasuhiko Saigou

IPC分类号： G06F12/08 ,  G11C11/4096

CPC分类号： G11C11/4096 ,  G06F12/0804

摘要： In a cache memory setup, a buffer register is provided to accommodate the data read from a data memory. Between the buffer register and the data memory is connected a selector. This selector selectively transfers to the buffer register part of the data read from the data memory. The remaining part of the data is replaced with appropriate data for transfer to the buffer register. This arrangement provides the cache memory with a partial-write function.

摘要翻译： 在缓存存储器设置中，提供缓冲寄存器以容纳从数据存储器读取的数据。 在缓冲寄存器和数据存储器之间连接一个选择器。 该选择器选择性地将从数据存储器读取的数据传送到缓冲寄存器部分。 数据的剩余部分被替换为适当的数据以传送到缓冲寄存器。 这种布置为高速缓冲存储器提供部分写入功能。

公开(公告)号：US5129074A

公开(公告)日：1992-07-07

申请号：US409672

申请日：1989-09-20

申请人： Takashi Kikuchi ,  Hiroshi Fukuta ,  Nobuo Saito ,  Oichi Atoda

发明人： Takashi Kikuchi ,  Hiroshi Fukuta ,  Nobuo Saito ,  Oichi Atoda

IPC分类号： G06F9/44 ,  G06F17/30

CPC分类号： G06F8/313 ,  G06F17/30

摘要： A data storage device for storing data strings each including units of data has a plurality of memory sections each for storing therein a table, a plurality of processor elements one provided for each of the tables and a controlling unit having an internal memory in which data strings are stored. The table contains a plurality of records each including a unit of data, a first index data representative of the number of units of data of a data string which the unit of data constitutes and a second index data unique to each individual data string. The processor elements access in parallel their associated tables under control of the control unit for data storage and data retrieval. The first and index data are generated by the controller for the purpose of data storage. For retrieval of data strings: a key data string is divided into units of data; retrieval keys are produced each from a combination of one of the divided units of data and a third index data representing the number of units of data of the key data string; second index data are retrieved in parallel in the tables of the data storage device with the retrieval keys so that a single second index data common to all of the retrieved second index data is found among them; and a data string corresponding to the found common second index data is outputted from the internal memory of the storage device.

摘要翻译： 一种用于存储包括数据单元的数据串的数据存储装置具有多个存储部分，每个存储部分用于在其中存储表格，为每个表格提供多个处理器元件，以及具有内部存储器的控制单元，其中数据串 被存储。 该表包含多个记录，每个记录包括数据单元，表示数据单元构成的数据串的数据单元数的第一索引数据和每个单独数据串唯一的第二索引数据。 处理器元件在用于数据存储和数据检索的控制单元的控制下并行访问其相关联的表。 第一和索引数据由控制器生成，用于数据存储。 用于检索数据串：一个关键数据串被分为数据单元; 从分割的数据单元之一的组合和表示密钥数据串的数据单元数的第三索引数据产生检索密钥; 在具有检索关键字的数据存储装置的表中并行地检索第二索引数据，使得在其中找到所有检索到的第二索引数据共同的单个第二索引数据; 并且从存储装置的内部存储器输出与所找到的公共第二索引数据相对应的数据串。

公开(公告)号：US5275691A

公开(公告)日：1994-01-04

申请号：US834358

申请日：1992-02-12

申请人： Hiroshi Fukuta ,  Akio Uesugi

发明人： Hiroshi Fukuta ,  Akio Uesugi

IPC分类号： B41N3/03 ,  C23F1/46 ,  C23D1/00

CPC分类号： C23F1/46 ,  B41N3/038

摘要： A method and apparatus for treating a surface of an aluminum substrate for a printing plate includes treating the substrate surface with a treatment liquid being circulated, separating and discharging aluminum ions from a portion of the treatment liquid, recovering a sodium hydroxide solution from the treatment liquid, mixing the recovered sodium hydroxide solution with the treatment liquid being circulated, and maintaining a predetermined concentration of aluminum ions in the treatment liquid to be used. A portion of the treatment liquid containing sodium aluminate solution is mixed with aluminum slag containing an amorphous aluminum hydroxide produced at the time of neutralization of a waste acid and a waste alkali produced during surface treatment to thereby supersaturate the sodium aluminate solution, crystallize the aluminum hydroxide, and recover the sodium hydroxide solution to be returned to a liquid control tank to maintain a predetermined concentration of aluminum ions in the treatment liquid. Further, the characteristics of the aluminum slag are changed to be usable as an industrially available aluminum hydroxide. Still further, a hydrolytic reaction is caused in a separated part of the treatment liquid. Preferably, the supersaturated aluminate solution is passed through a filter, so that aluminum hydroxide is crystallized from the sodium aluminate solution, and the sodium hydroxide solution is recovered.

摘要翻译： 一种用于处理印版的铝基板的表面的方法和装置，包括用处理液处理基板表面，处理液被循环，从处理液的一部分中分离和排出铝离子，从处理液中回收氢氧化钠溶液 将回收的氢氧化钠溶液与正在循环的处理液混合，并在待使用的处理液中保持预定浓度的铝离子。 将含有铝酸钠溶液的处理液的一部分与在中和废酸时产生的无定形氢氧化铝的铝渣和在表面处理期间产生的废碱混合，从而使铝酸钠溶液过饱和，使氢氧化铝结晶 并回收待返回到液体控制罐的氢氧化钠溶液以在处理液中保持预定浓度的铝离子。 此外，铝渣的特性被改变为可用作工业上可得到的氢氧化铝。 此外，在处理液的分离部分中引起水解反应。 优选地，过饱和铝酸盐溶液通过过滤器，使得氢氧化铝从铝酸钠溶液中结晶，并回收氢氧化钠溶液。

公开(公告)号：US5985165A

公开(公告)日：1999-11-16

申请号：US742153

申请日：1996-10-31

申请人： Hiroshi Fukuta ,  Tsutomu Kakei ,  Tadabumi Tomita ,  Hideki Miwa

发明人： Hiroshi Fukuta ,  Tsutomu Kakei ,  Tadabumi Tomita ,  Hideki Miwa

IPC分类号： B41N3/03 ,  C01F7/14 ,  C01F7/46 ,  C23F1/36 ,  C23F1/46 ,  B44C1/22 ,  C01F7/34

CPC分类号： C23F1/46 ,  B41N3/03 ,  C01F7/144 ,  C01P2006/80

摘要： The present invention allows the reproduction of a crystalline aluminum hydroxide having a high particle strength and a high purity which can find wide application such as abrasive from a supersaturated sodium aluminate solution which is being recycled in the production of aluminum hydroxide or lithographic printing plate. In a process for the purification of aluminum hydroxide which comprises the hydrolysis reaction of a supersaturated solution of sodium aluminate to crystallize aluminum hydroxide, the improvement which comprises the steps of keeping the temperature of a suspension formed by mixing a mother liquor having a total caustic soda concentration of from 50 to 700 g/l and an aluminum concentration or from 0 to 300 g/l with crystalline aluminum hydroxide at a range of from 10.degree. C. to 200.degree. C. for at least 1 to 48 hours, mixing the suspension with the supersaturated solution of sodium aluminate, and then causing the crystallization reaction at the crystallization reaction temperature.

摘要翻译： 本发明允许再生具有高颗粒强度和高纯度的结晶氢氧化铝，其可以从在氢氧化铝或平版印刷版的生产中再循环的过饱和铝酸钠溶液得到广泛的应用，例如磨料。 在包括铝酸钠的过饱和溶液的水解反应以氢氧化铝结晶的氢氧化铝的纯化方法中，包括如下步骤：将通过混合具有总苛性钠的母液混合形成的悬浮液的温度 浓度为50至700g / l，铝浓度为0至300g / l，结晶氢氧化铝的浓度为10至200℃至少1至48小时，将悬浮液 用过饱和的铝酸钠溶液，然后在结晶反应温度下引起结晶反应。

公开(公告)号：US20120218611A1

公开(公告)日：2012-08-30

申请号：US13465113

申请日：2012-05-07

申请人： Seiji Ikari ,  Hiroshi Fukuta ,  Takeshi Morino ,  Yoshinori Honguh ,  Masataka Shiratsuchi

发明人： Seiji Ikari ,  Hiroshi Fukuta ,  Takeshi Morino ,  Yoshinori Honguh ,  Masataka Shiratsuchi

IPC分类号： H04N1/04 ,  F21V7/05 ,  F21V7/04

CPC分类号： G01N21/8901 ,  G07D7/121 ,  G07D11/0084 ,  H04N1/0285 ,  H04N1/02865

摘要： According to one embodiment, illumination apparatus including, first light source module which includes light-emitting module that emits light, light-emitting module having line shape, and first reflection member which includes first reflection surface that reflects light emitted from light-emitting module of first light source module for predetermined range, wherein first reflection surface has cross section that has zigzag line shape including plurality of line segments running along standard oval, which has major axis that forms predetermined angle with direction perpendicular to predetermined range, in direction perpendicular to longitudinal direction of light-emitting module of first light source module.

摘要翻译： 根据一个实施例，照明装置包括：第一光源模块，其包括发光的发光模块，具有线形的发光模块;以及第一反射构件，其包括反射从第一反射面发射的光的第一反射面， 第一光源模块，其中第一反射表面具有锯齿线形状的横截面，包括沿着垂直于纵向方向的垂直于标准椭圆的多个线段，其具有与垂直于预定范围的方向垂直于预定范围的方向形成预定角度的长轴 第一光源模块的发光模块的方向。

公开(公告)号：US4725742A

公开(公告)日：1988-02-16

申请号：US865977

申请日：1986-05-22

申请人： Hiroshi Tachimori ,  Hiroshi Fukuta ,  Takeshi Fukazawa ,  Takao Ohkubo ,  Osamu Takahashi

发明人： Hiroshi Tachimori ,  Hiroshi Fukuta ,  Takeshi Fukazawa ,  Takao Ohkubo ,  Osamu Takahashi

IPC分类号： G11C17/18 ,  G11C8/10 ,  G11C11/34 ,  G11C11/413 ,  H03K19/177 ,  H03K19/017 ,  H03K19/094

CPC分类号： G11C8/10

摘要： A semiconductor integrated circuit device has an address decoder which is constructed of a plurality of MOSFETs implemented in a switch tree. The switch tree includes first and second switch tree portions which are controlled `on` and `off` by the same input signals. A first switch branch in the first switch tree portion, which is constructed of a comparatively small number of MOSFETs, and a second switch branch in the second switch tree portion, which is constructed of a comparatively large number of MOSFETs, are controlled `one` and `off` by the same input signal, while a second switch branch in the first switch tree portion, which is constructed of a comparatively large number of MOSFETs, and a first switch branch in the second switch tree portion, which is constructed of a comparatively small number of MOSFETs, are controlled `on` and `off` by the same input signal. This construction is effective to lessen an increase in the number of MOSFETs which are to be coupled to the input lines of the address decoder.

摘要翻译： 半导体集成电路器件具有由在开关树中实现的多个MOSFET构成的地址译码器。 开关树包括通过相同输入信号被控制为“开”和“关”的第一和第二开关树部分。 由较少数量的MOSFET构成的第一开关树部分中的第一开关分支和由相对大量的MOSFET构成的第二开关树部分中的第二开关分支被控制为“一” 并且通过相同的输入信号“关”，而由第二开关树部分构成的第一开关树部分中的第二开关分支和由第二开关树部分构成的第一开关分支，其由 相对较少数量的MOSFET通过相同的输入信号被控制为“开”和“关”。 这种结构对于减少要耦合到地址解码器的输入线的MOSFET的数量的增加是有效的。