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公开(公告)号：US08049270B2
公开(公告)日：2011-11-01
申请号：US11924175
申请日：2007-10-25
IPC分类号： H01L29/732
CPC分类号： H01L29/7813 , H01L29/0623 , H01L29/0634 , H01L29/1095 , H01L29/41766
摘要： This semiconductor device an epitaxial layer of a first conductivity type formed on a surface of the first semiconductor layer, and a base layer of a second conductivity type formed on a surface of the epitaxial layer. A diffusion layer of a first conductivity type is selectively formed in the base layer, and a trench penetrates the base layer to reach the epitaxial layer. A gate electrode is formed in the trench through the gate insulator film formed on the inner wall of the trench. A first buried diffusion layer of a second conductivity type is formed in the epitaxial layer deeper than the bottom of the gate electrode. A second buried diffusion layer connects the first buried diffusion layer and the base layer and has a resistance higher than that of the first buried diffusion layer.
摘要翻译： 该半导体器件形成在第一半导体层的表面上的第一导电类型的外延层和形成在外延层的表面上的第二导电类型的基极层。 在基底层中选择性地形成第一导电类型的扩散层，并且沟槽穿透基底层以到达外延层。 通过形成在沟槽内壁上的栅极绝缘膜，在沟槽中形成栅电极。 在比栅电极的底部更深的外延层中形成第二导电类型的第一掩埋扩散层。 第二掩埋扩散层连接第一掩埋扩散层和基底层，并且具有比第一掩埋扩散层的电阻高的电阻。
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公开(公告)号：US07485921B2
公开(公告)日：2009-02-03
申请号：US11674337
申请日：2007-02-13
IPC分类号： H01L29/78
CPC分类号： H01L29/7811 , H01L29/0615 , H01L29/0634 , H01L29/1095 , H01L29/402 , H01L29/41741 , H01L29/41766 , H01L29/7813
摘要： This semiconductor device comprises a first semiconductor layer of a first conductivity type, an epitaxial layer of a first conductivity type formed in the surface on the first semiconductor layer, and a base layer of a second conductivity type formed on the surface of the epitaxial layer. Column layers of a second conductivity type are repeatedly formed in the epitaxial layer under the base layer at a certain interval. Trenches are formed so as to penetrate the base layer to reach the epitaxial layer; and gate electrodes are formed in the trenches via a gate insulation film. A termination layer of a second conductivity type is formed on the epitaxial layer at an end region at the perimeter of the base layer. The termination layer is formed to have a junction depth larger than that of the base layer.
摘要翻译： 该半导体器件包括形成在第一半导体层表面上的第一导电类型的第一半导体层，第一导电类型的外延层和形成在外延层的表面上的第二导电类型的基极层。 第二导电类型的列层以一定间隔在基底层下的外延层中重复形成。 形成沟槽以穿透基底层以到达外延层; 并且栅电极经由栅极绝缘膜形成在沟槽中。 在基底层的周边的端部区域，在外延层上形成第二导电类型的端接层。 端接层形成为具有大于基底层的结深度的结深度。
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公开(公告)号：US20080099837A1
公开(公告)日：2008-05-01
申请号：US11924175
申请日：2007-10-25
IPC分类号： H01L29/94
CPC分类号： H01L29/7813 , H01L29/0623 , H01L29/0634 , H01L29/1095 , H01L29/41766
摘要： This semiconductor device an epitaxial layer of a first conductivity type formed on a surface of the first semiconductor layer, and a base layer of a second conductivity type formed on a surface of the epitaxial layer. A diffusion layer of a first conductivity type is selectively formed in the base layer, and a trench penetrates the base layer to reach the epitaxial layer. A gate electrode is formed in the trench through the gate insulator film formed on the inner wall of the trench. A first buried diffusion layer of a second conductivity type is formed in the epitaxial layer deeper than the bottom of the gate electrode. A second buried diffusion layer connects the first buried diffusion layer and the base layer and has a resistance higher than that of the first buried diffusion layer.
摘要翻译： 该半导体器件形成在第一半导体层的表面上的第一导电类型的外延层和形成在外延层的表面上的第二导电类型的基极层。 在基底层中选择性地形成第一导电类型的扩散层，并且沟槽穿透基底层以到达外延层。 通过形成在沟槽内壁上的栅极绝缘膜，在沟槽中形成栅电极。 在比栅电极的底部更深的外延层中形成第二导电类型的第一掩埋扩散层。 第二掩埋扩散层连接第一掩埋扩散层和基底层，并且具有比第一掩埋扩散层的电阻高的电阻。
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公开(公告)号：US20070262410A1
公开(公告)日：2007-11-15
申请号：US11742133
申请日：2007-04-30
IPC分类号： H01L29/00
CPC分类号： H01L29/872 , H01L27/0727 , H01L29/66143 , H01L29/8725
摘要： A semiconductor device includes: a semiconductor layer of a first conductivity type, a plurality of trenches provided on a major surface side of the semiconductor layer, an insulating film provided on an inner wall surface and on top of the trench, a conductive material surrounded by the insulating film and filling the trench, a first semiconductor region of a second conductivity type provided between the trenches, a second semiconductor region of the first conductivity type provided in a surface portion of the first semiconductor region, a mesa of the semiconductor layer provided between the trenches of a Schottky barrier diode region adjacent to a transistor region including the first semiconductor region and the second semiconductor region, a control electrode connected to the conductive material filling the trench of the transistor region and a main electrode provided in contact with a surface of the first semiconductor region, the second semiconductor region, a surface of the mesa and a part of the conductive material filling the trench of the Schottky barrier diode region. The part is exposed through the insulating film.
摘要翻译： 半导体器件包括：第一导电类型的半导体层，设置在半导体层的主表面侧的多个沟槽，设置在内壁表面上和沟槽顶部上的绝缘膜，由 绝缘膜并填充沟槽，设置在沟槽之间的第二导电类型的第一半导体区域，设置在第一半导体区域的表面部分中的第一导电类型的第二半导体区域，设置在第一半导体区域之间的半导体层的台面 与包括第一半导体区域和第二半导体区域的晶体管区域相邻的肖特基势垒二极管区域的沟槽，连接到填充晶体管区域的沟槽的导电材料的控制电极和与第一半导体区域和第二半导体区域的表面接触的主电极 第一半导体区域，第二半导体区域，台面的表面 以及填充肖特基势垒二极管区域的沟槽的导电材料的一部分。 该部件通过绝缘膜曝光。
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公开(公告)号：US20080035992A1
公开(公告)日：2008-02-14
申请号：US11836383
申请日：2007-08-09
申请人： Yusuke KAWAGUCHI , Yoshihiro Yamaguchi , Syotaro Ono , Akio Nakagawa , Miwako Akiyama , Kazuya Nakayama , Masakazu Yamaguchi
发明人： Yusuke KAWAGUCHI , Yoshihiro Yamaguchi , Syotaro Ono , Akio Nakagawa , Miwako Akiyama , Kazuya Nakayama , Masakazu Yamaguchi
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L21/2815 , H01L29/0634 , H01L29/0696 , H01L29/1095 , H01L29/41766 , H01L29/42356 , H01L29/4236 , H01L29/42368 , H01L29/42376 , H01L29/66734 , H01L29/7828
摘要： This semiconductor device comprises a drift layer of a first conductivity type formed on a drain layer of a first conductivity type, and a drain electrode electrically connected to the drain layer. A semiconductor base layer of a second conductivity type is formed in a surface of the drift layer, and a source region of a first conductivity type is further formed in the semiconductor base layer.A source electrode is electrically connected to the source region and a semiconductor base layer. Plural gate electrodes are formed through a gate insulation film so that a semiconductor base layer may be sandwiched by the gate electrodes. The width of the semiconductor base layer sandwiched by the gate electrodes is 0.3 micrometers or less.
摘要翻译： 该半导体器件包括形成在第一导电类型的漏极层上的第一导电类型的漂移层和电连接到漏极层的漏电极。 在漂移层的表面上形成第二导电类型的半导体基底层，并且在半导体基底层中进一步形成第一导电类型的源极区。 源电极电连接到源区和半导体基层。 多个栅电极通过栅极绝缘膜形成，使得半导体基底层可以被栅电极夹持。 被栅电极夹持的半导体基底层的宽度为0.3微米以下。
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公开(公告)号：US20070194375A1
公开(公告)日：2007-08-23
申请号：US11674337
申请日：2007-02-13
IPC分类号： H01L29/94
CPC分类号： H01L29/7811 , H01L29/0615 , H01L29/0634 , H01L29/1095 , H01L29/402 , H01L29/41741 , H01L29/41766 , H01L29/7813
摘要： This semiconductor device comprises a first semiconductor layer of a first conductivity type, an epitaxial layer of a first conductivity type formed in the surface on the first semiconductor layer, and a base layer of a second conductivity type formed on the surface of the epitaxial layer. Column layers of a second conductivity type are repeatedly formed in the epitaxial layer under the base layer at a certain interval. Trenches are formed so as to penetrate the base layer to reach the epitaxial layer; and gate electrodes are formed in the trenches via a gate insulation film. A termination layer of a second conductivity type is formed on the epitaxial layer at an end region at the perimeter of the base layer. The termination layer is formed to have a junction depth larger than that of the base layer.
摘要翻译： 该半导体器件包括形成在第一半导体层表面上的第一导电类型的第一半导体层，第一导电类型的外延层和形成在外延层的表面上的第二导电类型的基极层。 第二导电类型的列层以一定间隔在基底层下的外延层中重复形成。 形成沟槽以穿透基底层以到达外延层; 并且栅电极经由栅极绝缘膜形成在沟槽中。 在基底层的周边的端部区域，在外延层上形成第二导电类型的端接层。 端接层形成为具有大于基底层的结深度的结深度。
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公开(公告)号：US07663186B2
公开(公告)日：2010-02-16
申请号：US12118159
申请日：2008-05-09
申请人： Syotaro Ono , Yoshihiro Yamaguchi , Yusuke Kawaguchi , Kazutoshi Nakamura , Norio Yasuhara , Kenichi Matsushita , Shinichi Hodama , Akio Nakagawa
发明人： Syotaro Ono , Yoshihiro Yamaguchi , Yusuke Kawaguchi , Kazutoshi Nakamura , Norio Yasuhara , Kenichi Matsushita , Shinichi Hodama , Akio Nakagawa
CPC分类号： H01L29/7802 , H01L21/26586 , H01L29/0653 , H01L29/0696 , H01L29/0847 , H01L29/0878 , H01L29/1095 , H01L29/402 , H01L29/407 , H01L29/42368 , H01L29/42376 , H01L29/4238 , H01L29/66712 , H01L29/7809
摘要： A semiconductor device includes: a substrate, a surface portion thereof serving as a drain layer; a first main electrode connected to the drain layer; an epitaxial layer formed on the drain layer; a base layer formed on the epitaxial layer; a source layer formed in a base layer surface portion; an insulated trench sandwiched by base layers; a JFET layer formed on trench side walls; an LDD layer formed in a base layer surface portion and connected to the JFET layer around a top face of the trench; a control electrode formed on a gate insulating film formed on an LDD layer surface part, on surfaces of source layer end parts facing each other across the trench, and on a base layer region sandwiched by the LDD and source layers; and a second main electrode connected to the source and base layers sandwiching the control electrode.
摘要翻译： 半导体器件包括：衬底，用作漏极层的表面部分; 连接到漏极层的第一主电极; 形成在漏极层上的外延层; 形成在外延层上的基底层; 形成在基层表面部分中的源极层; 由基层夹住的绝缘沟槽; 形成在沟槽侧壁上的JFET层; LDD层，其形成在基底表面部分中并且围绕所述沟槽的顶面连接到所述JFET层; 形成在形成在LDD层表面部分上的栅极绝缘膜上的控制电极，在沟槽之间彼此面对的源极层部分的表面上以及由LDD和源极层夹持的基极层区域; 以及连接到夹持控制电极的源极和基极层的第二主电极。
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公开(公告)号：US06977414B2
公开(公告)日：2005-12-20
申请号：US10460407
申请日：2003-06-13
IPC分类号： H01L21/285 , H01L29/06 , H01L29/08 , H01L29/423 , H01L29/78 , H01L29/76
CPC分类号： H01L29/7816 , H01L21/28537 , H01L29/0619 , H01L29/0696 , H01L29/0847 , H01L29/0878 , H01L29/4238 , H01L29/7801 , H01L29/7802 , H01L29/7809
摘要： A semiconductor device comprises: a semiconductor layer of a first conductivity type; a pair of base regions of a second conductivity type selectively provided on a surface of the semiconductor layer; and source regions of a first conductivity type, each of the source regions being selectively provided on a surface of each of the base regions. The semiconductor device further comprises an electrical field reducing region of a second conductivity type selectively provided on the surface of the semiconductor layer between the pair of the base regions; a gate insulating film provided on the surface of the base regions; a pair of gate electrodes provided on the gate insulating film, each of the gate electrodes being provided on the surface of the base regions between the source region and the electrical field reducing region; and a source electrode connected to the source regions. The electrical field reducing region is isolated from both of the gate electrode and the source electrode.
摘要翻译： 半导体器件包括：第一导电类型的半导体层; 选择性地设置在半导体层的表面上的一对第二导电类型的基极区; 以及第一导电类型的源极区域，每个源区域选择性地设置在每个基极区域的表面上。 所述半导体器件还包括选择性地设置在所述一对基极区域之间的所述半导体层的表面上的第二导电类型的电场减小区域; 设置在所述基底区域的表面上的栅极绝缘膜; 设置在所述栅极绝缘膜上的一对栅电极，在所述源极区域和所述电场减少区域之间的所述基极区域的表面上设置各栅极电极; 以及与源极区域连接的源电极。 电场减少区域与栅极电极和源极电极隔离。
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9.发明授权Trench-gate semiconductor device and manufacturing method of trench-gate semiconductor device 有权沟槽栅半导体器件及沟槽栅极半导体器件的制造方法公开(公告)号：US07566933B2
公开(公告)日：2009-07-28
申请号：US11484664
申请日：2006-07-12
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L29/0696 , H01L29/1095 , H01L29/66734
摘要： Disclosed is a trench-gate semiconductor device including: a trench gate structure; a source layer having a first conductivity type, facing a gate electrode via a gate insulating film, and having a top plane; a base layer having a second conductivity type, being adjacent to the source layer, and facing the gate electrode via the gate insulating film; a semiconductor layer having the first conductivity type, being adjacent to the base layer, and facing the gate electrode via the gate insulating film without contacting the source layer; and a contact layer having the second conductivity type, contacting the source layer and base layer, having a top plane continuing with the top plane of the source layer, and having two or more peaks in an impurity concentration value profile in a depth direction from the top plane thereof, the peaks being positioned shallower than a formed depth of the source layer.
摘要翻译： 公开了一种沟槽栅半导体器件，包括：沟槽栅极结构; 具有第一导电类型的源极层，经由栅极绝缘膜面对栅电极，并具有顶面; 具有第二导电类型的基底层，与源极层相邻，并且经由栅极绝缘膜面对栅电极; 具有第一导电类型的半导体层，与基底层相邻，并且经由栅极绝缘膜面对栅电极而不接触源极层; 以及具有第二导电类型的接触层，与源极层和基极层接触，具有与源极层的顶部平面连续的顶面，并且具有两个或更多个沿着深度方向的杂质浓度值分布中的峰 峰位于比源层的形成深度浅的位置。
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公开(公告)号：US20070194372A1
公开(公告)日：2007-08-23
申请号：US11740045
申请日：2007-04-25
IPC分类号： H01L31/00
CPC分类号： H01L29/7813 , H01L29/1095
摘要： Disclosed is a trench MOSFET, including: a trench gate structure having a gate electrode and a gate insulating film; an n-type diffusion layer formed to face the gate electrode via the gate insulating film at an upper portion of the trench; a p-type base layer formed to face the gate electrode via the gate insulating film at a lower portion than the upper portion; an n-type epitaxial layer locating to face the gate electrode via the gate insulating film at a further lower portion than the lower portion; a metal layer formed departing from the trench in parallel with a depth direction of the trench, penetrating the n-type diffusion layer and the p-type base layer, to reach the n-type epitaxial layer; and a p-type layer with higher impurity concentration than the p-type base layer, locating to be in contact with the p-type base layer and the metal layer.
摘要翻译： 公开了一种沟槽MOSFET，其包括：具有栅极电极和栅极绝缘膜的沟槽栅极结构; 形成为在沟槽的上部经由栅极绝缘膜与栅电极对置的n型扩散层; p型基底层，其在比上部更低的一部分处经由栅极绝缘膜形成为面对栅电极; n型外延层，其定位成在比下部更下方的一部分经由栅极绝缘膜面对栅电极; 与沟槽的深度方向平行地形成的穿过n型扩散层和p型基底层的金属层，以到达n型外延层; 以及比p型基底层高的杂质浓度的p型层，与p型基底层和金属层接触。
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