公开(公告)号：US07541643B2

公开(公告)日：2009-06-02

申请号：US11399448

申请日：2006-04-07

申请人： Syotaro Ono ,  Wataru Saito ,  Yusuke Kawaguchi

发明人： Syotaro Ono ,  Wataru Saito ,  Yusuke Kawaguchi

IPC分类号： H01L29/76 ,  H01L29/94

CPC分类号： H01L29/7813 ,  H01L29/0615 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/402 ,  H01L29/41741 ,  H01L29/7811

摘要： This semiconductor device comprises a pillar layer including a first semiconductor pillar layer of a first conductivity type and a second semiconductor pillar layer of a second conductivity type formed alternately on a first semiconductor layer. At the same depth position in the device region and the end region, a difference between an impurity concentration [cm-3] of the second semiconductor pillar layer in the device region and that of the second semiconductor pillar layer in the end region is less than plus or minus 5%. A width W11 [um] of the first semiconductor pillar layer in the device region, a width W21 [um] of the second semiconductor pillar layer in the device region, a width W12 [um] of the first semiconductor pillar layer in the end region, and a width W22 [um] of the second semiconductor pillar layer in the end region, meet the relationship of W21/W11

摘要翻译： 该半导体器件包括：交替地在第一半导体层上形成的包括第一导电类型的第一半导体柱层和第二导电类型的第二半导体柱层的柱层。 在器件区域和端部区域的相同深度位置处，器件区域中的第二半导体柱层的杂质浓度[cm-3]与末端区域中的第二半导体柱层的杂质浓度[cm-3]之间的差小于 加或减5％。 器件区域中的第一半导体柱层的宽度W11 [μm]，器件区域中的第二半导体柱层的宽度W21 [μm]，端部区域中的第一半导体柱层的宽度W12 [μm] ，并且端部区域中的第二半导体柱层的宽度W22 [μm]满足W21 / W11

公开(公告)号：US20070018243A1

公开(公告)日：2007-01-25

申请号：US11485284

申请日：2006-07-13

申请人： Syotaro Ono ,  Wataru Saito ,  Yusuke Kawaguchi ,  Yoshihiro Yamaguchi

发明人： Syotaro Ono ,  Wataru Saito ,  Yusuke Kawaguchi ,  Yoshihiro Yamaguchi

IPC分类号： H01L29/94 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/4236 ,  H01L29/66727 ,  H01L29/66734

摘要： A semiconductor element is provided, comprising a first semiconductor layer of the first conduction type; and a pillar layer including first semiconductor pillars of the first conduction type and second semiconductor pillars of the second conduction type arranged periodically and alternately on the first semiconductor layer. A semiconductor base layer of the second conduction type is formed on the upper surface of the pillar layer, And a second semiconductor layer of the first conduction type is formed on the upper surface of the semiconductor base layer. A control electrode of the trench gate type is formed in a trench, which is formed in depth through the semiconductor base layer to the first semiconductor pillar. The control electrode is tapered such that the width thereof decreases with the distance from a second main electrode toward a first main electrode and the tip thereof locates almost at the center of the first semiconductor pillar.

摘要翻译： 提供一种半导体元件，包括第一导电类型的第一半导体层; 以及第一导电型的第一半导体柱和第二导电型的第二半导体柱在第一半导体层上周期性且交替地配置的柱层。 第二导电类型的半导体基层形成在柱层的上表面上，第一导电类型的第二半导体层形成在半导体基层的上表面上。 沟槽栅型的控制电极形成在沟槽中，该沟槽通过半导体基底层向第一半导体柱形成深度。 控制电极是锥形的，使得其宽度随着从第二主电极朝向第一主电极的距离而减小，并且其尖端几乎位于第一半导体柱的中心。

公开(公告)号：US20060231917A1

公开(公告)日：2006-10-19

申请号：US11399448

申请日：2006-04-07

申请人： Syotaro Ono ,  Wataru Saito ,  Yusuke Kawaguchi

发明人： Syotaro Ono ,  Wataru Saito ,  Yusuke Kawaguchi

IPC分类号： H01L29/00

CPC分类号： H01L29/7813 ,  H01L29/0615 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/402 ,  H01L29/41741 ,  H01L29/7811

摘要： This semiconductor device comprises a pillar layer including a first semiconductor pillar layer of a first conductivity type and a second semiconductor pillar layer of a second conductivity type formed alternately on a first semiconductor layer. At the same depth position in the device region and the end region, a difference between an impurity concentration [cm-3] of the second semiconductor pillar layer in the device region and that of the second semiconductor pillar layer in the end region is less than plus or minus 5%. A width W11 [um] of the first semiconductor pillar layer in the device region, a width W21 [um] of the second semiconductor pillar layer in the device region, a width W12 [um] of the first semiconductor pillar layer in the end region, and a width W22 [um] of the second semiconductor pillar layer in the end region, meet the relationship of W21/W11

公开(公告)号：US07479678B2

公开(公告)日：2009-01-20

申请号：US11485284

申请日：2006-07-13

申请人： Syotaro Ono ,  Wataru Saito ,  Yusuke Kawaguchi ,  Yoshihiro Yamaguchi

发明人： Syotaro Ono ,  Wataru Saito ,  Yusuke Kawaguchi ,  Yoshihiro Yamaguchi

IPC分类号： H01L29/76

CPC分类号： H01L29/7813 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/4236 ,  H01L29/66727 ,  H01L29/66734

摘要： A semiconductor element is provided, comprising a first semiconductor layer of the first conduction type; and a pillar layer including first semiconductor pillars of the first conduction type and second semiconductor pillars of the second conduction type arranged periodically and alternately on the first semiconductor layer. A semiconductor base layer of the second conduction type is formed on the upper surface of the pillar layer, And a second semiconductor layer of the first conduction type is formed on the upper surface of the semiconductor base layer. A control electrode of the trench gate type is formed in a trench, which is formed in depth through the semiconductor base layer to the first semiconductor pillar. The control electrode is tapered such that the width thereof decreases with the distance from a second main electrode toward a first main electrode and the tip thereof locates almost at the center of the first semiconductor pillar.

摘要翻译： 提供一种半导体元件，包括第一导电类型的第一半导体层; 以及第一导电型的第一半导体柱和第二导电型的第二半导体柱在第一半导体层上周期性且交替地配置的柱层。 第二导电类型的半导体基层形成在柱层的上表面上，第一导电类型的第二半导体层形成在半导体基层的上表面上。 沟槽栅型的控制电极形成在沟槽中，该沟槽通过半导体基底层向第一半导体柱形成深度。 控制电极是锥形的，使得其宽度随着从第二主电极朝向第一主电极的距离而减小，并且其尖端几乎位于第一半导体柱的中心。

公开(公告)号：US08829608B2

公开(公告)日：2014-09-09

申请号：US13051987

申请日：2011-03-18

申请人： Wataru Saito ,  Syotaro Ono ,  Shunji Taniuchi ,  Miho Watanabe ,  Hiroaki Yamashita

发明人： Wataru Saito ,  Syotaro Ono ,  Shunji Taniuchi ,  Miho Watanabe ,  Hiroaki Yamashita

IPC分类号： H01L29/78

CPC分类号： H01L29/7813 ,  H01L29/0865 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/42372 ,  H01L29/66734

摘要： According to one embodiment, a semiconductor device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of the first conductivity type, a third semiconductor layer of a second conductivity type, a fourth semiconductor layer of the second conductivity type, a fifth semiconductor layer of the first conductivity type, a control electrode, a first main electrode, a second main electrode, and a sixth semiconductor layer of the first conductivity type. The second semiconductor layer and the third semiconductor layer are alternately provided on the first semiconductor layer in a direction substantially parallel to a major surface of the first semiconductor layer. The fourth semiconductor layer is provided on the second semiconductor layer and the third semiconductor layer. The fifth semiconductor layer is selectively provided on a surface of the fourth semiconductor layer. The control electrode is provided in a trench via an insulating film. The trench penetrates through the fourth semiconductor layer from a surface of the fifth semiconductor layer and is in contact with the second semiconductor layer. The first main electrode is connected to the first semiconductor layer. The second main electrode is connected to the fourth semiconductor layer and the fifth semiconductor layer. The sixth semiconductor layer is provided between the fourth semiconductor layer and the second semiconductor layer. An impurity concentration of the sixth semiconductor layer is higher than an impurity concentration of the second semiconductor layer.

摘要翻译： 根据一个实施例，半导体器件包括第一导电类型的第一半导体层，第一导电类型的第二半导体层，第二导电类型的第三半导体层，第二导电类型的第四半导体层， 第一导电类型的第五半导体层，第一导电类型的控制电极，第一主电极，第二主电极和第六半导体层。 第二半导体层和第三半导体层在与第一半导体层的主表面大致平行的方向上交替地设置在第一半导体层上。 第四半导体层设置在第二半导体层和第三半导体层上。 第五半导体层选择性地设置在第四半导体层的表面上。 控制电极通过绝缘膜设置在沟槽中。 沟槽从第五半导体层的表面穿过第四半导体层并且与第二半导体层接触。 第一主电极连接到第一半导体层。 第二主电极连接到第四半导体层和第五半导体层。 第六半导体层设置在第四半导体层和第二半导体层之间。 第六半导体层的杂质浓度高于第二半导体层的杂质浓度。

公开(公告)号：US08772869B2

公开(公告)日：2014-07-08

申请号：US12050405

申请日：2008-03-18

申请人： Wataru Saito ,  Syotaro Ono

发明人： Wataru Saito ,  Syotaro Ono

IPC分类号： H01L29/66

CPC分类号： H01L29/7802 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/7811

摘要： A power semiconductor device includes: a first semiconductor layer; second and third semiconductor layers above and alternatively arranged along a direction parallel to an upper surface of the first semiconductor layer; and plural fourth semiconductor layers provided on some of immediately upper regions of the third semiconductor layer. An array period of the fourth semiconductor layers is larger than that of the second semiconductor layer. A thickness of part of the gate insulating film in an immediate upper region of a central portion between the fourth semiconductor layers is thicker than a thickness of part of the gate insulating film in an immediate upper region of the fourth semiconductor layers. Sheet impurity concentrations of the second and third semiconductor layers in the central portion are higher than a sheet impurity concentration of the third semiconductor layer in an immediately lower region of the fourth semiconductor layers.

摘要翻译： 功率半导体器件包括：第一半导体层; 第二和第三半导体层，并且沿着平行于第一半导体层的上表面的方向排列; 以及多个第四半导体层，设置在第三半导体层的一些上部区域上。 第四半导体层的阵列周期大于第二半导体层的阵列周期。 在第四半导体层之间的中心部分的直接上部区域中的栅极绝缘膜的一部分的厚度比在第四半导体层的直接上部区域中的栅极绝缘膜的一部分的厚度厚。 第二半导体层和第三半导体层在中心部分的片状杂质浓度高于第四半导体层的紧邻下部区域中的第三半导体层的片状杂质浓度。

公开(公告)号：US08610210B2

公开(公告)日：2013-12-17

申请号：US12840201

申请日：2010-07-20

申请人： Hiroshi Ohta ,  Yasuto Sumi ,  Kiyoshi Kimura ,  Wataru Sekine ,  Wataru Saito ,  Syotaro Ono ,  Munehisa Yabuzaki ,  Nana Hatano ,  Miho Watanabe

发明人： Hiroshi Ohta ,  Yasuto Sumi ,  Kiyoshi Kimura ,  Wataru Sekine ,  Wataru Saito ,  Syotaro Ono ,  Munehisa Yabuzaki ,  Nana Hatano ,  Miho Watanabe

IPC分类号： H01L29/66

CPC分类号： H01L29/66712 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/7811

摘要： According to one embodiment, a power semiconductor device includes a first semiconductor layer, and first, second and third semiconductor regions. The first semiconductor layer has a first conductivity type. The first semiconductor regions have a second conductivity type, and are formed with periodicity in a lateral direction in a second semiconductor layer of the first conductivity type. The second semiconductor layer is provided on a major surface of the first semiconductor layer in a device portion with a main current path formed in a vertical direction generally perpendicular to the major surface and in a terminal portion provided around the device portion. The second semiconductor region has the first conductivity type and is a portion of the second semiconductor layer sandwiched between adjacent ones of the first semiconductor regions. The third semiconductor regions have the second conductivity type and are provided below the first semiconductor regions in the terminal portion.

摘要翻译： 根据一个实施例，功率半导体器件包括第一半导体层以及第一，第二和第三半导体区域。 第一半导体层具有第一导电类型。 第一半导体区域具有第二导电类型，并且在第一导电类型的第二半导体层中在横向方向上形成周期性。 第二半导体层设置在器件部分的第一半导体层的主表面上，其主电流通道形成在大体上垂直于主表面的垂直方向上，以及设置在器件部分周围的端子部分中。 第二半导体区域具有第一导电类型，并且是夹在相邻的第一半导体区域中的第二半导体层的一部分。 第三半导体区域具有第二导电类型并且设置在端子部分中的第一半导体区域的下方。

公开(公告)号：US08188521B2

公开(公告)日：2012-05-29

申请号：US12728823

申请日：2010-03-22

申请人： Wataru Saito ,  Syotaro Ono ,  Munehisa Yabuzaki ,  Nana Hatano ,  Miho Watanabe

发明人： Wataru Saito ,  Syotaro Ono ,  Munehisa Yabuzaki ,  Nana Hatano ,  Miho Watanabe

IPC分类号： H01L29/739 ,  H01L29/78 ,  H01L29/08

CPC分类号： H01L29/7802 ,  H01L29/0619 ,  H01L29/0626 ,  H01L29/0634 ,  H01L29/0657 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/7808 ,  H01L29/7811 ,  H01L29/7828

摘要： A power semiconductor device has semiconductor layers, including: first layer of first type; second and third layers respectively of first and second types alternately on the first layer; fourth layers of second type on the third layers; fifth layers of first type on the fourth layer; sixth and seventh layers respectively of second and first types alternately on the second and third layers; a first electrode connected to the first layer; an insulation film on fourth, sixth, and seventh layers; a second electrode on fourth, sixth, and seventh layers via the insulation film; and a third electrode joined to fourth and fifth layers, wherein the sixth layers are connected to the fourth layers and one of the third layers between two fourth layers, and an impurity concentration of the third layers below the sixth layers is higher than that of the third layers under the fourth layers.

摘要翻译： 功率半导体器件具有半导体层，包括：第一层第一层; 第一和第二类型的第二和第三层交替地在第一层上; 第三层第四层第四层; 第四层第五层第一层; 第二层和第三层的第六层和第七层交替地在第二层和第三层上; 连接到第一层的第一电极; 第四层，第六层和第七层的绝缘膜; 经由绝缘膜的第四，第六和第七层上的第二电极; 以及连接到第四和第五层的第三电极，其中第六层连接到第四层，第二层之间的第三层之间的第二层之间的第二层和第三层之间的第三层的杂质浓度高于第六层的第三层 第四层第三层。

公开(公告)号：US08058688B2

公开(公告)日：2011-11-15

申请号：US11864101

申请日：2007-09-28

申请人： Syotaro Ono ,  Wataru Saito

发明人： Syotaro Ono ,  Wataru Saito

IPC分类号： H01L31/119

CPC分类号： H01L29/7802 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/66712

摘要： A semiconductor device includes: a semiconductor substrate; a first semiconductor layer of a first conductivity type provided on a major surface of the semiconductor substrate and having lower doping concentration than the semiconductor substrate; a plurality of first semiconductor column regions of the first conductivity type provided on the first semiconductor layer; a plurality of second semiconductor column regions of a second conductivity type provided on the first semiconductor layer, the second semiconductor column regions being adjacent to the first semiconductor column regions; a first semiconductor region; a second semiconductor region; a gate insulating film; a first main electrode; a second main electrode; and a control electrode. Doping concentrations in both the first and second semiconductor column region are low on the near side of the first semiconductor layer and high on the second main electrode side.

摘要翻译： 半导体器件包括：半导体衬底; 第一导电类型的第一半导体层设置在半导体衬底的主表面上并且具有比半导体衬底低的掺杂浓度; 设置在第一半导体层上的多个第一导电类型的第一半导体柱区域; 设置在所述第一半导体层上的第二导电类型的多个第二半导体柱区域，所述第二半导体柱区域与所述第一半导体柱区域相邻; 第一半导体区域; 第二半导体区域; 栅极绝缘膜; 第一主电极; 第二主电极; 和控制电极。 第一和第二半导体柱区域中的掺杂浓度在第一半导体层的近侧为低，在第二主电极侧为高。

公开(公告)号：US07812392B2

公开(公告)日：2010-10-12

申请号：US12138875

申请日：2008-06-13

申请人： Wataru Saito ,  Syotaro Ono

发明人： Wataru Saito ,  Syotaro Ono

IPC分类号： H01L29/94

CPC分类号： H01L29/7811 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0661 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41741

摘要： A semiconductor device includes a first first-conductivity-type semiconductor layer, a second first-conductivity-type semiconductor layer provided on a major surface of the first first-conductivity-type semiconductor layer; a third second-conductivity-type semiconductor layer being adjacent to the second first-conductivity-type semiconductor layer, provided on the major surface of the first first-conductivity-type semiconductor layer, and forming a periodic array structure in combination with the second first-conductivity-type semiconductor layer in a horizontal direction generally parallel to the major surface of the first first-conductivity-type semiconductor layer, and a sixth semiconductor layer located outside and adjacent to the periodic array structure of the second first-conductivity-type semiconductor layer and the third second-conductivity-type semiconductor layer, provided on the major surface of the first first-conductivity-type semiconductor layer, and having a lower impurity concentration than the periodic array structure. The amount of impurity in the outermost semiconductor layer of the first conductivity type or the second conductivity type adjacent to the sixth semiconductor layer in the periodic array structure is generally half the amount of impurity in the second first-conductivity-type semiconductor layer or the third second-conductivity-type semiconductor layer inside the outermost semiconductor layer.

摘要翻译： 半导体器件包括第一第一导电型半导体层，设置在第一第一导电型半导体层的主表面上的第二第一导电型半导体层; 与所述第二第一导电型半导体层相邻的第三第二导电型半导体层，设置在所述第一第一导电型半导体层的主表面上，并且与所述第二第一导电型半导体层的第二第一导电型半导体层 在与第一第一导电型半导体层的主表面大致平行的水平方向上的第一导电型半导体层以及与第二第一导电型半导体的周期性阵列结构的外侧相邻的第六半导体层 层和第三第二导电型半导体层，设置在第一第一导电型半导体层的主表面上，并且具有比周期性阵列结构低的杂质浓度。 在周期性排列结构中与第六半导体层相邻的第一导电类型或第二导电类型的最外半导体层中的杂质的量通常为第二第一导电型半导体层或第三导电型半导体层中杂质的量的一半 第二导电型半导体层。