公开(公告)号：US12092862B2

公开(公告)日：2024-09-17

申请号：US18327415

申请日：2023-06-01

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Mohammed Rabiul Islam ,  Stefan Rusu ,  Weiwei Song

IPC分类号： G02B6/12 ,  G02B6/13 ,  H01L23/00 ,  H01L25/00 ,  H01L21/48 ,  H01L23/538

CPC分类号： G02B6/12004 ,  G02B6/13 ,  H01L24/16 ,  H01L25/00 ,  G02B2006/12107 ,  G02B2006/12142 ,  H01L21/486 ,  H01L23/5385 ,  H01L2224/16227

摘要： A structure includes an optical interposer attached to a package substrate, wherein the optical interposer includes a silicon waveguide, a first photonic component optically coupled to the silicon waveguide, a second photonic component optically coupled to the silicon waveguide, and an interconnect structure extending over the silicon waveguide, over the first photonic component, and over the second photonic component, wherein the interconnect structure is electrically connected to the first photonic component and to the second photonic component, a first semiconductor device attached to the interconnect structure, wherein the first semiconductor device is electrically connected to the first photonic component through the interconnect structure, and a second semiconductor device attached to the interconnect structure, wherein the second semiconductor device is electrically connected to the second photonic component through the interconnect structure.

公开(公告)号：US12003239B2

公开(公告)日：2024-06-04

申请号：US17976187

申请日：2022-10-28

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Po-Chia Lai ,  Meng-Hung Shen ,  Chi-Lin Liu ,  Stefan Rusu ,  Yan-Hao Chen ,  Jerry Chang-Jui Kao

IPC分类号： H03K3/3562 ,  H03K3/012 ,  H03K3/0233 ,  H03K3/037 ,  H03K3/289 ,  H03K3/356

CPC分类号： H03K3/012 ,  H03K3/02332 ,  H03K3/0372 ,  H03K3/289 ,  H03K3/356104 ,  H03K3/3562 ,  H03K3/35625

摘要： A flip-flop circuit configured to latch an input signal to an output signal is disclosed. The circuit includes a first latch circuit; and a second latch circuit coupled to the first latch circuit. In some embodiments, in response to a clock signal, the first and second latch circuits are complementarily activated so as to latch the input signal to the output signal, and the first and second latch circuits each comprises at most two transistors configured to receive the clock signal.

公开(公告)号：US11860421B2

公开(公告)日：2024-01-02

申请号：US17097270

申请日：2020-11-13

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Weiwei Song ,  Chan-Hong Chern ,  Chewn-Pu Jou ,  Stefan Rusu ,  Min-Hsiang Hsu

IPC分类号： G02B6/30 ,  G02B6/26

CPC分类号： G02B6/305 ,  G02B6/262 ,  G02B6/30

摘要： An optical system with different optical coupling device configurations and a method of fabricating the same are disclosed. An optical system includes a substrate, a waveguide disposed on the substrate, an optical fiber optically coupled to the waveguide, and an optical coupling device disposed between the optical fiber and the waveguide. The optical coupling device configured to optically couple the optical fiber to the waveguide. The optical coupling device includes a dielectric layer disposed on the substrate, a semiconductor tapered structure disposed in a first horizontal plane within the dielectric layer, and a multi-tip dielectric structure disposed in a second horizontal plane within the dielectric layer. The first and second horizontal planes are different from each other.

公开(公告)号：US20220326443A1

公开(公告)日：2022-10-13

申请号：US17808813

申请日：2022-06-24

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Weiwei Song ,  Stefan Rusu ,  Chewn-Pu Jou ,  Huan-Neng Chen

IPC分类号： G02B6/293 ,  G02B6/122

摘要： A method includes etching a silicon layer to form a silicon slab and an upper silicon region over the silicon slab, and implanting the silicon slab and the upper silicon region to form a p-type region, an n-type region, and an intrinsic region between the p-type region and the n-type region. The method further includes etching the p-type region, the n-type region, and the intrinsic region to form a trench. The remaining portions of the upper silicon region form a Multi-Mode Interferometer (MMI) region. An epitaxy process is performed to grow a germanium region in the trench. Electrical connections are made to connect to the p-type region and the n-type region.

公开(公告)号：US11417596B2

公开(公告)日：2022-08-16

申请号：US16984297

申请日：2020-08-04

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Weiwei Song ,  Chan-Hong Chern ,  Feng-Wei Kuo ,  Lan-Chou Cho ,  Stefan Rusu

IPC分类号： H01L23/52 ,  H01L31/18 ,  H01L31/0232 ,  G02B6/43

摘要： In some embodiments, the present disclosure relates to an integrated chip that includes an insulator layer arranged over a substrate. Further, an upper routing structure is arranged over the insulator layer and is made of a semiconductor material. A lower optical routing structure is arranged below the substrate and is embedded in a lower dielectric structure. The integrated chip further includes an anti-reflective layer that is arranged below the substrate and directly contacts the substrate.

公开(公告)号：US20210271020A1

公开(公告)日：2021-09-02

申请号：US16803153

申请日：2020-02-27

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Mohammed Rabiul Islam ,  Stefan Rusu ,  Weiwei Song

IPC分类号： G02B6/12 ,  H01L23/538 ,  H01L23/00 ,  H01L21/48 ,  H01L25/00 ,  G02B6/13

摘要： A structure includes an optical interposer attached to a package substrate, wherein the optical interposer includes a silicon waveguide, a first photonic component optically coupled to the silicon waveguide, a second photonic component optically coupled to the silicon waveguide, and an interconnect structure extending over the silicon waveguide, over the first photonic component, and over the second photonic component, wherein the interconnect structure is electrically connected to the first photonic component and to the second photonic component, a first semiconductor device attached to the interconnect structure, wherein the first semiconductor device is electrically connected to the first photonic component through the interconnect structure, and a second semiconductor device attached to the interconnect structure, wherein the second semiconductor device is electrically connected to the second photonic component through the interconnect structure.

公开(公告)号：US10931264B2

公开(公告)日：2021-02-23

申请号：US16437541

申请日：2019-06-11

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Po-Chia Lai ,  Meng-Hung Shen ,  Chi-Lin Liu ,  Stefan Rusu ,  Yan-Hao Chen ,  Jerry Chang-Jui Kao

IPC分类号： H03K3/3562 ,  H03K3/012 ,  H03K3/0233 ,  H03K3/289 ,  H03K3/037 ,  H03K3/356

摘要： A flip-flop circuit configured to latch an input signal to an output signal is disclosed. The circuit includes a first latch circuit; and a second latch circuit coupled to the first latch circuit. In some embodiments, in response to a clock signal, the first and second latch circuits are complementarily activated so as to latch the input signal to the output signal, and the first and second latch circuits each comprises at most two transistors configured to receive the clock signal.

公开(公告)号：US10930554B2

公开(公告)日：2021-02-23

申请号：US16440825

申请日：2019-06-13

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Nick Samra ,  Stefan Rusu

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/535 ,  H01L29/78

摘要： A semiconductor device includes first, second, and third metallization layers, on top of one another, that are disposed above a substrate, wherein each of the first, second, and third metallization layer includes a respective metallization structure formed in a respective dielectric layer, wherein the second metallization layer is disposed between the first and third metallization layers; and a via tower structure that extends from the first metallization layer to the third metallization layer so as to electrically couple at least part of the respective metallization structures of the first and third metallization layers.

公开(公告)号：US20210013179A1

公开(公告)日：2021-01-14

申请号：US17030420

申请日：2020-09-24

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Nick Samra ,  Alan Roth ,  Eric Soenen ,  Stefan Rusu ,  Paul Ranucci

IPC分类号： H01L25/065 ,  H01L21/66 ,  H01L25/18 ,  H01L23/00 ,  G05F1/595 ,  H01L21/82 ,  H01L49/02 ,  G05F1/59 ,  H01L23/522

摘要： A device includes a semiconductor die. The semiconductor die has formed thereon a plurality of multi-phase voltage regulator modules of the same design formed on a common semiconductor substrate.

公开(公告)号：US10403600B2

公开(公告)日：2019-09-03

申请号：US15782885

申请日：2017-10-13

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Nick Samra ,  Alan Roth ,  Eric Soenen ,  Stefan Rusu ,  Paul Ranucci

IPC分类号： G05F1/59 ,  H01L25/065 ,  H01L21/66 ,  H01L25/18 ,  H01L23/00 ,  G05F1/595 ,  H01L21/82 ,  H01L49/02

摘要： A device includes a semiconductor die. The semiconductor die has formed thereon a plurality of multi-phase voltage regulator modules of the same design formed on a common semiconductor substrate.