-
公开(公告)号:US20220357669A1
公开(公告)日:2022-11-10
申请号:US17566563
申请日:2021-12-30
发明人: Shih-Ming CHANG , Ken-Hsien HSIEH , Yu-Tien SHEN
IPC分类号: G03F7/20 , G06F30/398 , G03F1/22
摘要: A semiconductor processing system includes a first photolithography system and a second photolithography system. The semiconductor processing system includes a layout database that stores a plurality of layouts indicating features to be formed in a wafer. The semiconductor processing system includes a layout analyzer that analyzes the layouts and selects either the first photolithography system or the second photolithography system based on dimensions of features in the layouts.
-
公开(公告)号:US20210286274A1
公开(公告)日:2021-09-16
申请号:US17301215
申请日:2021-03-29
发明人: Chih-Jie LEE , Shih-Chun HUANG , Shih-Ming CHANG , Ken-Hsien HSIEH , Yung-Sung YEN , Ru-Gun LIU
IPC分类号: G03F9/00
摘要: A method of performing a lithography process includes providing a test pattern. The test pattern includes a first set of lines arranged at a first pitch, a second set of lines arranged at the first pitch, and further includes at least one reference line between the first set of lines and the second set of lines. The test pattern is exposed with a radiation source providing an asymmetric, monopole illumination profile to form a test pattern structure on a substrate. The test pattern structure is then measured and a measured distance correlated to an offset of a lithography parameter. A lithography process is adjusted based on the offset of the lithography parameter.
-
3.
公开(公告)号:US20240248387A1
公开(公告)日:2024-07-25
申请号:US18313203
申请日:2023-05-05
CPC分类号: G03F1/22 , G03F1/52 , G03F1/80 , G03F7/70033 , G03F7/702
摘要: A first bright field reticle and a second bright field reticle are utilized for a double exposure EUV photolithography process in which exposure areas of the first and second bright field reticles overlap. The first and second reticles each include, respectively, a substrate, a reflective multilayer on the substrate, a main pattern of absorption material on the reflective multilayer, a black border area, and an additional absorption area of the absorption material between the black border and the main pattern.
-
公开(公告)号:US20210132504A1
公开(公告)日:2021-05-06
申请号:US16886509
申请日:2020-05-28
发明人: Ken-Hsien HSIEH , Shih-Ming CHANG , Wen LO , Wei-Shuo SU , Hua-Tai LIN
IPC分类号: G03F7/20
摘要: In one example, an apparatus includes an extreme ultraviolet illumination source and an illuminator. The extreme ultraviolet illumination source is arranged to generate a beam of extreme ultraviolet illumination to pattern a resist layer on a substrate. The illuminator is arranged to direct the beam of extreme ultraviolet illumination onto a surface of a photomask. In one example, the illuminator includes a field facet mirror and a pupil facet mirror. The field facet mirror includes a first plurality of facets arranged to split the beam of extreme ultraviolet illumination into a plurality of light channels. The pupil facet mirror includes a second plurality of facets arranged to direct the plurality of light channels onto the surface of the photomask. The distribution of the second plurality of facets is denser at a periphery of the pupil facet mirror than at a center of the pupil facet mirror.
-
公开(公告)号:US20180164695A1
公开(公告)日:2018-06-14
申请号:US15689244
申请日:2017-08-29
发明人: Ken-Hsien HSIEH , Wen-Li CHENG , Pai-Wei WANG , Ru-Gun LIU , Chih-Ming LAI
CPC分类号: G03F7/70283 , G03F1/22 , G03F1/36 , G03F1/68 , G03F1/70 , G03F7/70433 , G03F7/70466 , G03F7/705 , G06F17/5045 , G06F17/5081
摘要: A multiple patterning decomposition method for IC is provided. Features of layout of IC are decomposed into a plurality of nodes. The nodes are classified to assign a plurality of first and second links between the nodes. First and second pseudo colors are assigned to a pair of nodes of each first link. The second links having a pair of nodes both corresponding to the first or second pseudo color are identified. The nodes of the first links are uncolored. A first real color is assigned to the two uncolored nodes of the identified second links in each of the networks. A second real color is assigned to the uncolored nodes connected to the nodes corresponding to the first real color through the first links. First and second masks are formed according to the nodes corresponding to the first and second real colors, respectively.
-
公开(公告)号:US20220365452A1
公开(公告)日:2022-11-17
申请号:US17815155
申请日:2022-07-26
发明人: Chih-Jie LEE , Shih-Chun HUANG , Shih-Ming CHANG , Ken-Hsien HSIEH , Yung-Sung YEN , Ru-Gun LIU
IPC分类号: G03F9/00
摘要: A method of performing a lithography process includes providing a test pattern. The test pattern includes a first set of lines arranged at a first pitch, a second set of lines arranged at the first pitch, and further includes at least one reference line between the first set of lines and the second set of lines. The test pattern is exposed with a radiation source providing an asymmetric, monopole illumination profile to form a test pattern structure on a substrate. The test pattern structure is then measured and a measured distance correlated to an offset of a lithography parameter. A lithography process is adjusted based on the offset of the lithography parameter.
-
公开(公告)号:US20210013048A1
公开(公告)日:2021-01-14
申请号:US17034043
申请日:2020-09-28
发明人: Ru-Gun LIU , Chih-Ming LAI , Wei-Liang LIN , Yung-Sung YEN , Ken-Hsien HSIEH , Chin-Hsiang LIN
IPC分类号: H01L21/311 , H01L21/027 , H01L21/768
摘要: In a method of forming a groove pattern extending in a first axis in an underlying layer over a semiconductor substrate, a first opening is formed in the underlying layer, and the first opening is extended in the first axis by directional etching to form the groove pattern.
-
8.
公开(公告)号:US20140237435A1
公开(公告)日:2014-08-21
申请号:US14267013
申请日:2014-05-01
发明人: Huang-Yu CHEN , Tsong-Hua OU , Ken-Hsien HSIEH , Chin-Hsiung HSU
IPC分类号: G06F17/50
CPC分类号: G06F17/5081 , G06F17/5072 , G06F2217/12
摘要: A method identifies, as an independent node, any node representing a circuit pattern in any odd loop of a layout of a region of a layer of an IC that is not included in any other odd loop of the layout. The layer is to have a plurality of circuit patterns to be patterned using at least three photomasks. The method identifies, as a safe independent node, any independent node not closer than a threshold distance from any other independent nodes in another odd loop of the layout. The layout is modified, if the circuit patterns in the layout include any odd loop without any safe independent node, so that that after the modifying, each odd loop has at least one safe independent node.
摘要翻译: 一种方法将作为独立节点的任何节点表示在不包括在布局的任何其它奇数循环中的IC层的区域的布局的任何奇数循环中的电路图案。 该层将具有使用至少三个光掩模进行图案化的多个电路图案。 该方法将安全独立节点识别为距离布局的另一个奇数循环中任何其他独立节点不超过阈值距离的任何独立节点。 布局被修改,如果布局中的电路图案包括没有任何安全独立节点的任何奇数循环,使得在修改之后,每个奇数循环至少有一个安全独立节点。
-
公开(公告)号:US20140210100A1
公开(公告)日:2014-07-31
申请号:US13755326
申请日:2013-01-31
发明人: You-Cheng XIAO , Wei Min CHAN , Ken-Hsien HSIEH
IPC分类号: H01L21/768 , G06F17/50 , H01L23/48
CPC分类号: H01L23/5226 , G06F17/5068 , G06F17/5077 , G06F2217/78 , H01L21/76838 , H01L23/481 , H01L23/528 , H01L27/11 , H01L2924/0002 , H01L2924/00
摘要: A method comprises: forming a plurality of reference voltage patterns in a first layer of a semiconductor substrate using a first mask, the reference voltage patterns including alternating first reference voltage patterns and second reference voltage patterns; and forming a plurality of signal patterns in the first layer of the semiconductor substrate using a second mask, ones of the plurality of signal patterns located between successive pairs of reference voltage patterns.
摘要翻译: 一种方法包括:使用第一掩模在半导体衬底的第一层中形成多个参考电压图案,所述参考电压图案包括交替的第一参考电压图案和第二参考电压图案; 以及使用第二掩模在所述半导体衬底的第一层中形成多个信号图案,所述多个信号图案中的一个信号图案位于连续的参考电压图案对之间。
-
公开(公告)号:US20220399272A1
公开(公告)日:2022-12-15
申请号:US17566564
申请日:2021-12-30
发明人: Yu-Tien SHEN , Ken-Hsien HSIEH , Shih-Ming CHANG
IPC分类号: H01L23/528 , H01L21/311 , H01L21/768
摘要: A semiconductor processing system includes a layout database that stores a plurality of layouts indicating features to be formed in a wafer. The semiconductor processing system includes a layout analyzer that analyzes the layouts and determines, for each layout, whether a non-perpendicular particle bombardment process should be utilized in conjunction with a photolithography process for forming the features of the layout in a wafer.
-
-
-
-
-
-
-
-
-