公开(公告)号：US20230326756A1

公开(公告)日：2023-10-12

申请号：US18333100

申请日：2023-06-12

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yu-Chen CHANG ,  Chien-Wen LAI ,  Chih-Min HSIAO

IPC: H01L21/033 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/308

CPC classification number: H01L21/0337 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/31051

Abstract: A method for forming a semiconductor structure includes forming first mandrels over a target layer. The method for forming a semiconductor structure also includes forming a first opening to cut off one of the first mandrels. The method for forming a semiconductor structure also includes forming a spacer layer over the first mandrels. The method for forming a semiconductor structure also includes forming second mandrels over the spacer layer and between the first mandrels. The method for forming a semiconductor structure also includes forming a second opening to cut off one of the second mandrels. The method for forming a semiconductor structure also includes etching the spacer layer. The method for forming a semiconductor structure also includes etching the target layer.

公开(公告)号：US20220237357A1

公开(公告)日：2022-07-28

申请号：US17334320

申请日：2021-05-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Shih-Wei PENG ,  Chih-Min HSIAO ,  Ching-Hsu CHANG ,  Jiann-Tyng TZENG

IPC: G06F30/392 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  G06F30/394 ,  G03F1/42

Abstract: A method of generating an integrated circuit (IC) layout diagram includes obtaining a grid of intersecting first and second pluralities of tracks corresponding to adjacent metal layers, determining that first and second pitches of the respective first and second pluralities of tracks conform to a first rule, applying a via positioning pattern to the grid whereby via regions are restricted to alternating diagonal grid lines, positioning via regions at some or all of the grid intersections of the alternating diagonal grid lines, and generating the IC layout diagram including the via regions positioned along the alternating diagonal grid lines.

公开(公告)号：US20220130968A1

公开(公告)日：2022-04-28

申请号：US17313576

申请日：2021-05-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Shih-Wei PENG ,  Chih-Min HSIAO ,  Jiann-Tyng TZENG

IPC: H01L29/417 ,  H01L23/528 ,  H01L23/522 ,  H01L29/40 ,  H01L21/768 ,  H01L21/311

Abstract: An integrated circuit includes a set of power rails, a set of active regions, a first set of conductive lines and a first and a second set of vias. The set of power rails is configured to supply a first or second supply voltage, and is on a first level of a back-side of a substrate. The set of active regions is a second level of a front-side of the substrate. The first set of conductive lines extend in a second direction and overlap the set of active regions. The first set of vias is between and electrically couples the set of active regions and the first set of conductive lines together. The second set of vias is between and electrically couples the first set of conductive lines and the set of power rails together.

公开(公告)号：US20240162142A1

公开(公告)日：2024-05-16

申请号：US18421552

申请日：2024-01-24

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Shih-Wei PENG ,  Chih-Min HSIAO ,  Ching-Hsu CHANG ,  Jiann-Tyng TZENG

IPC: H01L23/522 ,  G03F1/42 ,  G06F30/392 ,  G06F30/394

CPC classification number: H01L23/5226 ,  G03F1/42 ,  G06F30/392 ,  G06F30/394 ,  H01L23/528

Abstract: A method of manufacturing a plurality of via structures includes providing an integrated circuit (IC) photo mask including via features and assist features positioned exclusively along alternating diagonal grid lines of a grid, aligning the IC photo mask with first metal segments of a first metal layer of a semiconductor substrate, the first metal segments having a first spacing corresponding to a first pitch of the grid, performing one or more photolithography processes including the IC photo mask, thereby defining via structure locations corresponding to the via features, and forming via structures at the defined via structure locations.

公开(公告)号：US20230282514A1

公开(公告)日：2023-09-07

申请号：US17832205

申请日：2022-06-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Shih-Wei PENG ,  Chih-Min HSIAO ,  Chien-Wen LAI ,  Jiann-Tyng TZENG ,  Yu-Luen DENG

IPC: H01L21/768 ,  H01L23/528

CPC classification number: H01L21/76879 ,  H01L23/528

Abstract: Provided is a method for manufacturing integrated circuit (IC) devices including the operations of forming a first metal pattern (Mx) on a semiconductor substrate, forming a first via pattern (Vx) on the first metal pattern using an area selective deposition (ASD) that includes first and second vias formed adjacent opposed edges or terminal portions of the first metal pattern, and forming a second metal pattern (Mx+1) on the first via pattern with substantially no pattern overlap to form a zero enclosure and wherein a pair of adjacent vias are separated by a distance corresponding to the smallest end-to-end metal pattern spacing permitted under a set of design rules applied during the design of the IC devices.

公开(公告)号：US20220262647A1

公开(公告)日：2022-08-18

申请号：US17735073

申请日：2022-05-02

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chih-Min HSIAO ,  Chih-Ming LAI ,  Chien-Wen LAI ,  Ya Hui CHANG ,  Ru-Gun LIU

IPC: H01L21/311 ,  H01L21/768 ,  H01L23/528 ,  H01L23/522

Abstract: A method for manufacturing a semiconductor device includes depositing a hard mask layer on an upper surface of an insulating layer. The hard mask layer is etched to form an opening in the hard mask layer. A via recess is formed in the insulating layer through the opening. A first photoresist layer is formed on the hard mask layer and in the via recess. The first photoresist layer is etched to form a photoresist plug in the via recess. Two opposite sides of the opening are etched to remove portions of the hard mask layer and thereby a portion of the upper surface of the insulating layer is exposed. The photoresist plug is removed. Metal is deposited in the via recess and on the exposed surface of the insulating layer. The metal is patterned.

公开(公告)号：US20240371653A1

公开(公告)日：2024-11-07

申请号：US18778571

申请日：2024-07-19

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Min HSIAO ,  Chih-Ming LAI ,  Chien-Wen LAI ,  Ya Hui CHANG ,  Ru-Gun LIU

IPC: H01L21/311 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528

Abstract: A method for manufacturing a semiconductor device includes depositing a hard mask layer on an upper surface of an insulating layer. The hard mask layer is etched to form an opening in the hard mask layer. A via recess is formed in the insulating layer through the opening. A first photoresist layer is formed on the hard mask layer and in the via recess. The first photoresist layer is etched to form a photoresist plug in the via recess. Two opposite sides of the opening are etched to remove portions of the hard mask layer and thereby a portion of the upper surface of the insulating layer is exposed. The photoresist plug is removed. Metal is deposited in the via recess and on the exposed surface of the insulating layer. The metal is patterned.

公开(公告)号：US20240297042A1

公开(公告)日：2024-09-05

申请号：US18660980

申请日：2024-05-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Min HSIAO ,  Chien-Wen LAI ,  Shih-chun HUANG ,  Yung-Sung YEN ,  Chih-Ming LAI ,  Ru-Gun LIU

IPC: H01L21/033 ,  H10B10/00

CPC classification number: H01L21/0337 ,  H01L21/0332 ,  H01L21/0338 ,  H10B10/00

Abstract: A method of defining a pattern includes forming a plurality of cut shapes and a first plurality of openings within a first layer of a multi-layer hard mask to expose first portions of the second layer. A plurality of etch stops is formed by implanting an etch rate modifying species in a portion of the plurality of cut shapes. The first layer is directionally etched at the plurality of cut shapes such that the plurality of etch stops remain. A spacer layer is formed on the first layer and the first portions. A second plurality of openings is formed within the spacer layer to expose second portions of the second layer. The spacer layer is directionally etched to remove the spacer layer from sidewalls of the plurality of etch stops. Portions of the second layer exposed through the first plurality of openings and the second plurality of openings are etched.

公开(公告)号：US20230377900A1

公开(公告)日：2023-11-23

申请号：US18227858

申请日：2023-07-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chih-Min HSIAO ,  Chih-Ming LAI ,  Chien-Wen LAI ,  Ya HuI CHANG ,  Ru-Gun LIU

IPC: H01L21/311 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L21/31144 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L21/76808

Abstract: A method for manufacturing a semiconductor device includes depositing a hard mask layer on an upper surface of an insulating layer. The hard mask layer is etched to form an opening in the hard mask layer. A via recess is formed in the insulating layer through the opening. A first photoresist layer is formed on the hard mask layer and in the via recess. The first photoresist layer is etched to form a photoresist plug in the via recess. Two opposite sides of the opening are etched to remove portions of the hard mask layer and thereby a portion of the upper surface of the insulating layer is exposed. The photoresist plug is removed. Metal is deposited in the via recess and on the exposed surface of the insulating layer. The metal is patterned.

公开(公告)号：US20230230836A1

公开(公告)日：2023-07-20

申请号：US18123820

申请日：2023-03-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chih-Min HSIAO ,  Chien-Wen Lai ,  Shih-chun Huang ,  Yung-Sung Yen ,  Chih-Ming Lai ,  Ru-Gun Liu

IPC: H01L21/033

CPC classification number: H01L21/0337 ,  H01L21/0332 ,  H01L21/0338 ,  H10B10/00

Abstract: A method of defining a pattern includes forming a plurality of cut shapes and a first plurality of openings within a first layer of a multi-layer hard mask to expose first portions of the second layer. A plurality of etch stops is formed by implanting an etch rate modifying species in a portion of the plurality of cut shapes. The first layer is directionally etched at the plurality of cut shapes such that the plurality of etch stops remain. A spacer layer is formed on the first layer and the first portions. A second plurality of openings is formed within the spacer layer to expose second portions of the second layer. The spacer layer is directionally etched to remove the spacer layer from sidewalls of the plurality of etch stops. Portions of the second layer exposed through the first plurality of openings and the second plurality of openings are etched.