公开(公告)号：US12125712B2

公开(公告)日：2024-10-22

申请号：US18227858

申请日：2023-07-28

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chih-Min Hsiao ,  Chih-Ming Lai ,  Chien-Wen Lai ,  Ya Hui Chang ,  Ru-Gun Liu

IPC分类号： H01L21/311 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528

CPC分类号： H01L21/31144 ,  H01L21/76808 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528

摘要： A method for manufacturing a semiconductor device includes depositing a hard mask layer on an upper surface of an insulating layer. The hard mask layer is etched to form an opening in the hard mask layer. A via recess is formed in the insulating layer through the opening. A first photoresist layer is formed on the hard mask layer and in the via recess. The first photoresist layer is etched to form a photoresist plug in the via recess. Two opposite sides of the opening are etched to remove portions of the hard mask layer and thereby a portion of the upper surface of the insulating layer is exposed. The photoresist plug is removed. Metal is deposited in the via recess and on the exposed surface of the insulating layer. The metal is patterned.

公开(公告)号：US12014926B2

公开(公告)日：2024-06-18

申请号：US18123820

申请日：2023-03-20

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chih-Min Hsiao ,  Chien-Wen Lai ,  Shih-Chun Huang ,  Yung-Sung Yen ,  Chih-Ming Lai ,  Ru-Gun Liu

IPC分类号： H01L21/033 ,  H10B10/00

CPC分类号： H01L21/0337 ,  H01L21/0332 ,  H01L21/0338 ,  H10B10/00

摘要： A method of defining a pattern includes forming a plurality of cut shapes and a first plurality of openings within a first layer of a multi-layer hard mask to expose first portions of the second layer. A plurality of etch stops is formed by implanting an etch rate modifying species in a portion of the plurality of cut shapes. The first layer is directionally etched at the plurality of cut shapes such that the plurality of etch stops remain. A spacer layer is formed on the first layer and the first portions. A second plurality of openings is formed within the spacer layer to expose second portions of the second layer. The spacer layer is directionally etched to remove the spacer layer from sidewalls of the plurality of etch stops. Portions of the second layer exposed through the first plurality of openings and the second plurality of openings are etched.

公开(公告)号：US11798812B2

公开(公告)日：2023-10-24

申请号：US17735073

申请日：2022-05-02

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chih-Min Hsiao ,  Chih-Ming Lai ,  Chien-Wen Lai ,  Ya Hui Chang ,  Ru-Gun Liu

IPC分类号： H01L21/311 ,  H01L21/768 ,  H01L23/528 ,  H01L23/522

CPC分类号： H01L21/31144 ,  H01L21/76808 ,  H01L21/76877 ,  H01L23/528 ,  H01L23/5226

摘要： A method for manufacturing a semiconductor device includes depositing a hard mask layer on an upper surface of an insulating layer. The hard mask layer is etched to form an opening in the hard mask layer. A via recess is formed in the insulating layer through the opening. A first photoresist layer is formed on the hard mask layer and in the via recess. The first photoresist layer is etched to form a photoresist plug in the via recess. Two opposite sides of the opening are etched to remove portions of the hard mask layer and thereby a portion of the upper surface of the insulating layer is exposed. The photoresist plug is removed. Metal is deposited in the via recess and on the exposed surface of the insulating layer. The metal is patterned.

公开(公告)号：US20230230836A1

公开(公告)日：2023-07-20

申请号：US18123820

申请日：2023-03-20

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chih-Min HSIAO ,  Chien-Wen Lai ,  Shih-chun Huang ,  Yung-Sung Yen ,  Chih-Ming Lai ,  Ru-Gun Liu

IPC分类号： H01L21/033

CPC分类号： H01L21/0337 ,  H01L21/0332 ,  H01L21/0338 ,  H10B10/00

摘要： A method of defining a pattern includes forming a plurality of cut shapes and a first plurality of openings within a first layer of a multi-layer hard mask to expose first portions of the second layer. A plurality of etch stops is formed by implanting an etch rate modifying species in a portion of the plurality of cut shapes. The first layer is directionally etched at the plurality of cut shapes such that the plurality of etch stops remain. A spacer layer is formed on the first layer and the first portions. A second plurality of openings is formed within the spacer layer to expose second portions of the second layer. The spacer layer is directionally etched to remove the spacer layer from sidewalls of the plurality of etch stops. Portions of the second layer exposed through the first plurality of openings and the second plurality of openings are etched.

公开(公告)号：US11748549B2

公开(公告)日：2023-09-05

申请号：US17236832

申请日：2021-04-21

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chin-Min Huang ,  Bo-Han Chen ,  Cherng-Shyan Tsay ,  Chien-Wen Lai ,  Hua-Tai Lin ,  Chia-Cheng Chang ,  Lun-Wen Yeh ,  Shun-Shing Yang

IPC分类号： G06F30/398 ,  G03F1/36 ,  G03F1/70

CPC分类号： G06F30/398 ,  G03F1/36 ,  G03F1/70

摘要： Various integrated circuit (IC) design methods are disclosed herein. An exemplary method includes receiving an IC design layout having an IC feature to be formed on a wafer using a lithography process and inserting a spacing in the IC feature, thereby generating a modified IC design layout that divides the IC feature into a first main feature and a second main feature separated by the spacing. The spacing has a sub-resolution dimension, such that the IC feature does not include the spacing when formed on the wafer by the lithography process using the modified IC design layout. A mask can be fabricated based on the modified IC design layout, wherein the mask includes the first main feature and the second main feature separated by the spacing. A lithography process can be performed using the mask to form the IC feature (without the spacing) on a wafer.

公开(公告)号：US11699589B2

公开(公告)日：2023-07-11

申请号：US17389602

申请日：2021-07-30

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yu-Chen Chang ,  Chien-Wen Lai ,  Chih-Min Hsiao

IPC分类号： H01L21/033 ,  H01L21/308 ,  H01L21/3213

CPC分类号： H01L21/0337 ,  H01L21/0332 ,  H01L21/0338 ,  H01L21/308 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/32139 ,  Y10S438/947 ,  Y10S438/95

摘要： A method for forming a patterned mask layer is provided. The method includes forming a first layer over a substrate. The method includes forming a first strip structure and a second strip structure over the first layer. The method includes forming a spacer layer conformally covering the first strip structure, the second strip structure, and the first layer. The method includes forming a block structure in the first trench. The method includes removing a first portion of the spacer layer, which is under the first trench and not covered by the block structure, and a second portion of the spacer layer, which is over the first strip structure and the second strip structure. The method includes forming a third strip structure in the second trench and the third trench. The method includes removing the block structure. The method includes removing the spacer layer.

公开(公告)号：US20210240907A1

公开(公告)日：2021-08-05

申请号：US17236832

申请日：2021-04-21

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chin-Min Huang ,  Bo-Han Chen ,  Cherng-Shyan Tsay ,  Chien-Wen Lai ,  Hua-Tai Lin ,  Chia-Cheng Chang ,  Lun-Wen Yeh ,  Shun-Shing Yang

IPC分类号： G06F30/398 ,  G03F1/36 ,  G03F1/70

摘要： Various integrated circuit (IC) design methods are disclosed herein. An exemplary method includes receiving an IC design layout having an IC feature to be formed on a wafer using a lithography process and inserting a spacing in the IC feature, thereby generating a modified IC design layout that divides the IC feature into a first main feature and a second main feature separated by the spacing. The spacing has a sub-resolution dimension, such that the IC feature does not include the spacing when formed on the wafer by the lithography process using the modified IC design layout. A mask can be fabricated based on the modified IC design layout, wherein the mask includes the first main feature and the second main feature separated by the spacing. A lithography process can be performed using the mask to form the IC feature (without the spacing) on a wafer.

公开(公告)号：US11715638B2

公开(公告)日：2023-08-01

申请号：US17378419

申请日：2021-07-16

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yu-Chen Chang ,  Chien-Wen Lai ,  Chih-Min Hsiao

IPC分类号： H01L21/033 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/308

CPC分类号： H01L21/0337 ,  H01L21/3086 ,  H01L21/31051 ,  H01L21/31144

摘要： A method for forming a semiconductor structure includes forming a hard mask layer over a target layer. The method also includes forming first mandrels over the hard mask layer. The method also includes forming a first opening in the first mandrels. The method also includes depositing a spacer layer over the hard mask layer and the first mandrels. The method also includes depositing a second mandrel material over the spacer layer. The method also includes planarizing the second mandrel material. The method also includes forming a second opening in the second mandrel material. The method also includes patterning and etching the second mandrel material to form second mandrels. The method also includes etching the spacer layer. The method also includes etching the hard mask layer and the target layer.

公开(公告)号：US12080544B2

公开(公告)日：2024-09-03

申请号：US17394977

申请日：2021-08-05

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Yu-Chen Chang ,  Chien-Wen Lai ,  Chih-Min Hsiao

IPC分类号： H01L21/02 ,  H01L21/304 ,  H01L25/065

CPC分类号： H01L21/02021 ,  H01L21/02043 ,  H01L21/304 ,  H01L25/0657 ,  H01L2221/68327

摘要： A method includes bonding a front side surface of a first wafer to a second wafer; performing a multi-trimming process on the first and second wafers from a back side surface of the first wafer, the multi-trimming process comprising: performing a first trimming step from the back side surface of the first wafer to cut through a periphery of the first wafer; performing a second trimming step on the second wafer to partially cut a periphery of the second wafer to form a first step-like structure; and performing a third trimming step on the second wafer to partially cut the periphery of the second wafer to form a second step-like structure connecting down from the first step-like structure; after performing the multi-trimming process, forming a coating material at least over the periphery of the second wafer.

公开(公告)号：US11862465B2

公开(公告)日：2024-01-02

申请号：US17589315

申请日：2022-01-31

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Shih-Chun Huang ,  Chiu-Hsiang Chen ,  Ya-Wen Yeh ,  Yu-Tien Shen ,  Po-Chin Chang ,  Chien-Wen Lai ,  Wei-Liang Lin ,  Ya Hui Chang ,  Yung-Sung Yen ,  Li-Te Lin ,  Pinyen Lin ,  Ru-Gun Liu ,  Chin-Hsiang Lin

IPC分类号： H01L21/033 ,  H01L21/027 ,  H01L21/311 ,  H01L21/02 ,  H01L21/265 ,  H01L21/3115

CPC分类号： H01L21/0338 ,  H01L21/0217 ,  H01L21/0274 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/26586 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/31155

摘要： A method of manufacturing a semiconductor device including operations of forming a first hard mask over an underlying layer on a substrate by a photolithographic and etching method, forming a sidewall spacer pattern having a first sidewall portion and a second sidewall portion on opposing sides of the first hard mask, etching the first sidewall portion, etching the first hard mask and leaving the second sidewall portion bridging a gap of the etched first hard mask, and processing the underlying layer using the second hard mask.