公开(公告)号：US20240393690A1

公开(公告)日：2024-11-28

申请号：US18790799

申请日：2024-07-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yu-Tse LAI ,  Minfeng CHEN ,  Ya Hui CHANG

IPC: G03F7/09 ,  G03F7/20 ,  H01L21/027 ,  H01L21/311

Abstract: A method of manufacturing a semiconductor device includes forming a target layer over a substrate and forming a chemically amplified photoresist layer over the target layer. The method further includes forming a metallic photoresist layer over the chemically amplified photoresist layer, and selectively exposing the metallic photoresist layer to actinic radiation. The method also includes removing portions of the metallic photoresist layer that were not exposed to the actinic radiation to form a patterned metallic photoresist layer, and flood exposing the patterned metallic photoresist layer and the chemically amplified photoresist layer to extreme ultraviolet (XUV) radiation. The method further includes removing portions of the chemically amplified photoresist layer not covered by the patterned metallic photoresist layer and the patterned metallic photoresist layer to form a patterned chemically amplified photoresist layer exposing portions of the target layer.

公开(公告)号：US20240371653A1

公开(公告)日：2024-11-07

申请号：US18778571

申请日：2024-07-19

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Min HSIAO ,  Chih-Ming LAI ,  Chien-Wen LAI ,  Ya Hui CHANG ,  Ru-Gun LIU

IPC: H01L21/311 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528

Abstract: A method for manufacturing a semiconductor device includes depositing a hard mask layer on an upper surface of an insulating layer. The hard mask layer is etched to form an opening in the hard mask layer. A via recess is formed in the insulating layer through the opening. A first photoresist layer is formed on the hard mask layer and in the via recess. The first photoresist layer is etched to form a photoresist plug in the via recess. Two opposite sides of the opening are etched to remove portions of the hard mask layer and thereby a portion of the upper surface of the insulating layer is exposed. The photoresist plug is removed. Metal is deposited in the via recess and on the exposed surface of the insulating layer. The metal is patterned.

公开(公告)号：US20250044708A1

公开(公告)日：2025-02-06

申请号：US18920346

申请日：2024-10-18

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ru-Gun LIU ,  Huicheng CHANG ,  Chia-Cheng CHEN ,  Jyu-Horng SHIEH ,  Liang-Yin CHEN ,  Shu-Huei SUEN ,  Wei-Liang LIN ,  Ya Hui CHANG ,  Yi-Nien SU ,  Yung-Sung YEN ,  Chia-Fong CHANG ,  Ya-Wen YEH ,  Yu-Tien SHEN

IPC: G03F7/00 ,  G03F1/22 ,  G03F1/36 ,  G03F1/70 ,  G03F7/40 ,  H01L21/027

Abstract: In a method of forming a pattern, a photo resist layer is formed over an underlying layer, the photo resist layer is exposed to an actinic radiation carrying pattern information, the exposed photo resist layer is developed to form a developed resist pattern, a directional etching operation is applied to the developed resist pattern to form a trimmed resist pattern, and the underlying layer is patterned using the trimmed resist pattern as an etching mask.

公开(公告)号：US20250038072A1

公开(公告)日：2025-01-30

申请号：US18360178

申请日：2023-07-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Hsin-Yuan LEE ,  Chih-Kai YANG ,  Ken-Hsien HSIEH ,  Ya Hui CHANG

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/367

Abstract: A semiconductor die includes a substrate, a semiconductor device, a back-end-of-line (BEOL) structure, and a heat dissipation structure. The substrate includes a device region and a non-device region. The BEOL structure includes a plurality of metallization layers. Each of the metallization layers includes a dielectric layer, interconnect features, and metal patterns. The interconnect features is in the dielectric layer and over the device region of the substrate, in which the interconnect features are electrically connected with the semiconductor device. The metal patterns are in the dielectric layer and over the non-device region of the substrate, in which the metal patterns are electrically isolated from the semiconductor device. The heat dissipation structure is over the non-device region of the substrate and extending through at least two of the metallization layers, in which the heat dissipation structure is in contact with the metal patterns of one of the metallization layers.

公开(公告)号：US20220157605A1

公开(公告)日：2022-05-19

申请号：US17589315

申请日：2022-01-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Shih-Chun HUANG ,  Chiu-Hsiang CHEN ,  Ya-Wen YEH ,  Yu-Tien SHEN ,  Po-Chin CHANG ,  Chien-Wen LAI ,  Wei-Liang LIN ,  Ya Hui CHANG ,  Yung-Sung YEN ,  Li-Te LIN ,  Pinyen LIN ,  Ru-Gun LIU ,  Chin-Hsiang LIN

IPC: H01L21/033 ,  H01L21/027 ,  H01L21/311 ,  H01L21/02 ,  H01L21/265

Abstract: A method of manufacturing a semiconductor device including operations of forming a first hard mask over an underlying layer on a substrate by a photolithographic and etching method, forming a sidewall spacer pattern having a first sidewall portion and a second sidewall portion on opposing sides of the first hard mask, etching the first sidewall portion, etching the first hard mask and leaving the second sidewall portion bridging a gap of the etched first hard mask, and processing the underlying layer using the second hard mask.

公开(公告)号：US20230305381A1

公开(公告)日：2023-09-28

申请号：US17833823

申请日：2022-06-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Wei-Shuo SU ,  Yu-Tse LAI ,  Sheng-Min WANG ,  Ken-Hsien HSIEH ,  Chieh-Jen CHENG ,  Ya Hui CHANG

IPC: G03F1/24 ,  G03F1/42

CPC classification number: G03F1/24 ,  G03F1/42

Abstract: A photo mask for an extreme ultraviolet (EUV) lithography includes a mask alignment mark for aligning the photo mask to an EUV lithography tool, and sub-resolution assist patterns disposed around the mask alignment mark. A dimension of the sub-resolution assist patterns is in a range from 10 nm to 50 nm.

公开(公告)号：US20220262647A1

公开(公告)日：2022-08-18

申请号：US17735073

申请日：2022-05-02

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chih-Min HSIAO ,  Chih-Ming LAI ,  Chien-Wen LAI ,  Ya Hui CHANG ,  Ru-Gun LIU

IPC: H01L21/311 ,  H01L21/768 ,  H01L23/528 ,  H01L23/522

Abstract: A method for manufacturing a semiconductor device includes depositing a hard mask layer on an upper surface of an insulating layer. The hard mask layer is etched to form an opening in the hard mask layer. A via recess is formed in the insulating layer through the opening. A first photoresist layer is formed on the hard mask layer and in the via recess. The first photoresist layer is etched to form a photoresist plug in the via recess. Two opposite sides of the opening are etched to remove portions of the hard mask layer and thereby a portion of the upper surface of the insulating layer is exposed. The photoresist plug is removed. Metal is deposited in the via recess and on the exposed surface of the insulating layer. The metal is patterned.