公开(公告)号：US10755938B2

公开(公告)日：2020-08-25

申请号：US15996789

申请日：2018-06-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Chi-Cheng Hung ,  Yu-Sheng Wang ,  Ting-Siang Su ,  Ching-Hwanq Su

IPC: H01L21/285 ,  H01L29/423 ,  C23C14/18 ,  H01L21/28 ,  C23C14/02 ,  H01L29/78 ,  H01L29/49 ,  H01L29/51 ,  H01L21/768

Abstract: The present disclosure provides a semiconductor structure, including an active region with a first surface; an isolated region having a second surface, surrounding the active region, the first surface being higher than the second surface; and a metal gate having a plurality of metal layers disposed over the first surface and the second surface. A ratio of a thinnest portion and a thickest portion of at least one of the plurality of metal layers is greater than about 40%.

公开(公告)号：US20190035916A1

公开(公告)日：2019-01-31

申请号：US15705034

申请日：2017-09-14

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shih-Hang Chiu ,  Chung-Chiang Wu ,  Chia-Ching Lee ,  Da-Yuan Lee ,  Ching-Hwanq Su

IPC: H01L29/66 ,  H01L21/3065 ,  H01L21/762 ,  H01L21/28 ,  H01L21/225

Abstract: A method includes forming a dummy gate structure over a semiconductor fin, forming a dielectric layer on opposing sides of the dummy gate structure, and removing the dummy gate structure to form a recess in the dielectric layer. The method further includes forming a gate dielectric layer and at least one conductive layer successively over sidewalls and a bottom of the recess, and treating the gate dielectric layer and the at least one conductive layer with a chemical containing fluoride (F).

公开(公告)号：US09396953B2

公开(公告)日：2016-07-19

申请号：US14213395

申请日：2014-03-14

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chi-Cheng Hung ,  Kuan-Ting Liu ,  Yu-Sheng Wang ,  Ching-Hwanq Su

IPC: H01L21/285 ,  H01L21/3105 ,  H01L21/28 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H01L29/49 ,  H01L29/165

CPC classification number: H01L21/2855 ,  H01L21/28088 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

Abstract: A method includes forming a dummy gate stack over a semiconductor substrate, wherein the semiconductor substrate is comprised in a wafer. The method further includes removing the dummy gate stack to form a recess, forming a gate dielectric layer in the recess, and forming a metal layer in the recess. The metal layer is over the gate dielectric layer. The formation of the metal layer includes placing the wafer against a target, applying a DC power to the target, and applying an RF power to the target, wherein the DC power and the RF power are applied simultaneously. A remaining portion of the recess is then filled with metallic materials, wherein the metallic materials are overlying the metal layer.

Abstract translation: 一种方法包括在半导体衬底上形成虚拟栅极堆叠，其中半导体衬底包含在晶片中。 该方法还包括去除虚拟栅极叠层以形成凹槽，在凹槽中形成栅极电介质层，并在凹槽中形成金属层。 金属层在栅介质层上。 金属层的形成包括将晶片放置在目标上，向目标物施加DC电力，并向目标物施加RF功率，其中同时施加DC电力和RF功率。 然后用金属材料填充凹部的剩余部分，其中金属材料覆盖在金属层上。

公开(公告)号：US20240096883A1

公开(公告)日：2024-03-21

申请号：US18522265

申请日：2023-11-29

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ji-Cheng Chen ,  Ching-Hwanq Su ,  Kuan-Ting Liu ,  Shih-Hang Chiu

IPC: H01L27/088 ,  H01L21/02 ,  H01L21/28 ,  H01L21/285 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L27/0886 ,  H01L21/02205 ,  H01L21/02211 ,  H01L21/28088 ,  H01L21/28556 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823462 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/42372 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/66545 ,  H01L21/31053 ,  H01L29/517

Abstract: A method of manufacturing a gate structure includes at least the following steps. A gate dielectric layer is formed. A work function layer is deposited on the gate dielectric layer. A barrier layer is formed on the work function layer. A metal layer is deposited on the barrier layer to introduce fluorine atoms into the barrier layer. The barrier layer is formed by at least the following steps. A first TiN layer is formed on the work function layer. A top portion of the first TiN layer is converted into a trapping layer, and the trapping layer includes silicon atoms or aluminum atoms. A second TiN layer is formed on the trapping layer.

公开(公告)号：US11309213B2

公开(公告)日：2022-04-19

申请号：US16940246

申请日：2020-07-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Yu-Hsiang Liao ,  Ya-Huei Li ,  Li-Wei Chu ,  Chun-Wen Nieh ,  Hung-Yi Huang ,  Chih-Wei Chang ,  Ching-Hwanq Su

IPC: H01L21/76 ,  H01L21/768 ,  H01L21/285 ,  H01L29/40 ,  H01L29/78 ,  H01L29/66

Abstract: A method for manufacturing a semiconductor structure includes following operations. A sacrificial layer is formed over the conductive layer, wherein the sacrificial layer includes a first sacrificial portion over the first conductive portion, and a second sacrificial portion over the second conductive portion, and a first thickness of the first sacrificial portion is larger than a second thickness of the second sacrificial portion. The first sacrificial portion and the second sacrificial portion of the sacrificial layer, and the second conductive portion of the conductive layer are removed.

公开(公告)号：US11289578B2

公开(公告)日：2022-03-29

申请号：US16398922

申请日：2019-04-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsin-Yi Lee ,  Ya-Huei Li ,  Da-Yuan Lee ,  Ching-Hwanq Su

IPC: H01L29/40 ,  H01L27/088 ,  H01L21/3215 ,  H01L21/8234 ,  H01L21/285 ,  H01L29/49

Abstract: A method includes forming a gate dielectric comprising a portion extending on a semiconductor region, forming a barrier layer comprising a portion extending over the portion of the gate dielectric, forming a work function tuning layer comprising a portion over the portion of the barrier layer, doping a doping element into the work function tuning layer, removing the portion of the work function tuning layer, thinning the portion of the barrier layer, and forming a work function layer over the portion of the barrier layer.

公开(公告)号：US11056395B2

公开(公告)日：2021-07-06

申请号：US16549195

申请日：2019-08-23

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chung-Chiang Wu ,  Hung-Chin Chung ,  Hsien-Ming Lee ,  Chien-Hao Chen ,  Ching-Hwanq Su

IPC: H01L21/8234 ,  H01L27/088

Abstract: Semiconductor devices and methods of manufacturing semiconductor devices with differing threshold voltages are provided. In embodiments the threshold voltages of individual semiconductor devices are tuned through the removal and placement of differing materials within each of the individual gate stacks within a replacement gate process, whereby the removal and placement helps keep the overall process window for a fill material large enough to allow for a complete fill.

公开(公告)号：US10756087B2

公开(公告)日：2020-08-25

申请号：US16010366

申请日：2018-06-15

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chung-Chiang Wu ,  Shih-Hang Chiu ,  Chih-Chang Hung ,  I-Wei Yang ,  Shu-Yuan Ku ,  Cheng-Lung Hung ,  Da-Yuan Lee ,  Ching-Hwanq Su

IPC: H01L27/088 ,  H01L29/06 ,  H01L27/11 ,  H01L21/8234 ,  H01L29/66

Abstract: A method includes forming a first semiconductor fin in a substrate, forming a metal gate structure over the first semiconductor fin, removing a portion of the metal gate structure to form a first recess in the metal gate structure that is laterally separated from the first semiconductor fin by a first distance, wherein the first distance is determined according to a first desired threshold voltage associated with the first semiconductor fin, and filling the recess with a dielectric material.

公开(公告)号：US20200091315A1

公开(公告)日：2020-03-19

申请号：US16690455

申请日：2019-11-21

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yu-Sheng Wang ,  Chi-Cheng Hung ,  Chia-Ching Lee ,  Ching-Hwanq Su

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/51 ,  H01L29/49 ,  H01L29/08 ,  H01L29/06 ,  H01L21/762 ,  H01L21/28

Abstract: A semiconductor device and method of manufacturing are provided. In an embodiment a first nucleation layer is formed within an opening for a gate-last process. The first nucleation layer is treated in order to remove undesired oxygen by exposing the first nucleation layer to a precursor that reacts with the oxygen to form a gas. A second nucleation layer is then formed, and a remainder of the opening is filled with a bulk conductive material.

公开(公告)号：US10157785B2

公开(公告)日：2018-12-18

申请号：US15583789

申请日：2017-05-01

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yu-Sheng Wang ,  Chi-Cheng Hung ,  Ching-Hwanq Su ,  Liang-Yueh Ou Yang ,  Ming-Hsing Tsai ,  Yu-Ting Lin

IPC: H01L21/768 ,  H01L21/288 ,  H01L29/66 ,  H01L23/532

Abstract: A method includes forming a first opening in a dielectric layer over a substrate, lining sidewalls and a bottom of the first opening with a conductive barrier layer, and depositing a seed layer over the conductive barrier layer. The method further includes treating the seed layer with a plasma process, and filling the first opening with a conductive material after the treating the seed layer.