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11 条记录 (耗时 0.031 秒)

    Memory array and method of forming the same
    3.
    发明授权
    Memory array and method of forming the same 有权

    公开(公告)号：US10121520B2

    公开(公告)日：2018-11-06

    申请号：US15960815

    申请日：2018-04-24

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Yu-Hao Hu ,  Yi-Tzu Chen ,  Hao-I Yang ,  Cheng-Jen Chang ,  Geng-Cing Lin

    IPC分类号： G11C5/14 ,  G11C7/06 ,  G11C7/12 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L27/105

    摘要： A memory array includes a first column of memory cells, a second column of memory cells, a first pre-charge circuit, a second pre-charge circuit and a set of input output circuits. The first column of memory cells includes a first bit line, a first word line and a first bit line bar. The second column of memory cells includes the first bit line bar, a second word line and a second bit line. The first pre-charge circuit is coupled to the first bit line. The second pre-charge circuit is coupled to the first bit line bar. The first column of memory cells and the second column of memory cells are configured to share the first bit line bar. The first bit line and the first bit line bar are in a first plane. At least a portion of the first word line and at least a portion of the second word line are in a second plane intersecting the first plane.

    Pulling devices for driving data lines
    4.
    发明授权
    Pulling devices for driving data lines 有权
    拉动设备来驱动数据线

    公开(公告)号：US09484084B2

    公开(公告)日：2016-11-01

    申请号：US14920209

    申请日：2015-10-22

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Hao-I Yang ,  Chia-En Huang ,  Cheng Hung Lee ,  Geng-Cing Lin ,  Jung-Ping Yang

    IPC分类号： G11C7/00 ,  G11C11/419 ,  G11C7/10 ,  G11C8/06 ,  G11C8/18 ,  G11C7/18 ,  G11C7/22

    CPC分类号： G11C11/419 ,  G11C7/10 ,  G11C7/12 ,  G11C7/18 ,  G11C7/22 ,  G11C8/06 ,  G11C8/18 ,  H01L27/1104 ,  H01L27/1116

    摘要： A circuit includes a first data line, a second data line, a first pulling device, a second pulling device, a third pulling device, and a fourth pulling device. The first pulling device is configured to be activated or deactivated responsive to a first control signal; and is configured to pull a first signal at the first data line toward a voltage level of a first voltage based on a second signal at the second data line when the first pulling device is activated. The second pulling device is configured to be activated or deactivated responsive to a second control signal; and is configured to pull the second signal at the second data line toward the voltage level of the first voltage based on the first signal at the first data line when the second pulling device is activated.

    摘要翻译： 电路包括第一数据线，第二数据线，第一牵引装置，第二牵引装置，第三牵引装置和第四牵引装置。 第一牵引装置被配置为响应于第一控制信号被激活或停用; 并且被配置为当第一牵引装置被激活时，基于第二数据线处的第二信号将第一数据线处的第一信号拉向第一电压的电压电平。 第二牵引装置被配置为响应于第二控制信号被激活或停用; 并且被配置为当第二拉动装置被启动时，基于第一数据线处的第一信号将第二数据线处的第二信号拉向第一电压的电压电平。

    Power switch control in a memory device
    5.
    发明授权
    Power switch control in a memory device 有权

    公开(公告)号：US11133039B2

    公开(公告)日：2021-09-28

    申请号：US16594779

    申请日：2019-10-07

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Hao-I Yang ,  Cheng Hung Lee ,  Chen-Lin Yang ,  Yu-Hao Hsu

    IPC分类号： G11C5/14 ,  G11C11/417

    摘要： A power switch control circuit includes a supply rail configured to supply power to a memory array. A first header switch couples the supply rail to a first power supply that corresponds to a first power domain. A second header switch couples the supply rail to a second power supply that corresponds to a second power domain. A control circuit is configured to receive a select signal and a shutdown signal, and to output control signals to the first and second header switches to selectively couple the first and second header switches to the first and second power supplies, respectively, in response to the select signal and the shutdown signal. The control circuit is configured to output the control signals to the first and second header switches to disconnect both the first and second header switches from the first and second power supplies in response to the shutdown signal and irrespective of the select signal.

    Clock circuit and method of operating the same
    6.
    发明授权
    Clock circuit and method of operating the same 有权

    公开(公告)号：US10951200B2

    公开(公告)日：2021-03-16

    申请号：US16800981

    申请日：2020-02-25

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Hao-I Yang ,  Cheng Hung Lee ,  Chen-Lin Yang ,  Chiting Cheng ,  Fu-An Wu ,  Yangsyu Lin

    IPC分类号： H03K3/037 ,  G11C11/412 ,  G06F1/04 ,  G11C7/22 ,  G11C11/417

    摘要： A clock circuit includes a latch circuit, a memory state latch circuit, a memory state trigger circuit and a clock trigger circuit. The latch circuit is configured to latch an enable signal, and to generate a latch output signal based on a first clock signal. The memory state latch circuit is coupled to the latch circuit, and generates an output clock signal responsive to a first control signal. The memory state trigger circuit is coupled to the memory state latch circuit, and adjusts the output clock signal responsive to the latch output signal or a reset signal. The clock trigger circuit is coupled to the latch circuit and the memory state trigger circuit by a first node, configured to generate the first clock signal responsive to a second clock signal, and configured to control the latch circuit and the memory state trigger circuit based on the first clock signal.

    Clock generating circuit and method of operating the same
    7.
    发明授权
    Clock generating circuit and method of operating the same 有权

    公开(公告)号：US10340897B2

    公开(公告)日：2019-07-02

    申请号：US16039824

    申请日：2018-07-19

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Hao-I Yang ,  Cheng Hung Lee ,  Chen-Lin Yang ,  Chiting Cheng ,  Fu-An Wu ,  Yangsyu Lin

    IPC分类号： H03K3/037 ,  G11C11/412

    摘要： A clock circuit includes a first latch, second latch, first trigger circuit and clock trigger circuit. The first latch generates a first latch output signal based on a first control signal, an enable signal and an output clock signal. The second latch is coupled to the first latch, and configured to generate the output clock signal responsive to a second control signal. The first trigger circuit is coupled to the first latch and the second latch, and configured to adjust the output clock signal responsive to at least the first latch output signal or a reset signal. The clock trigger circuit is coupled to the first latch and the first trigger circuit by a first node, is configured to generate the first control signal responsive to an input clock signal, and configured to control the first latch and the first trigger circuit based on at least the first control signal.

    Clock circuit and method of operating the same
    9.
    发明授权
    Clock circuit and method of operating the same 有权

    公开(公告)号：US11323101B2

    公开(公告)日：2022-05-03

    申请号：US17200195

    申请日：2021-03-12

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Hao-I Yang ,  Fu-An Wu ,  Yangsyu Lin ,  Chiting Cheng ,  Cheng Hung Lee ,  Chen-Lin Yang

    IPC分类号： G06F1/04 ,  H03K3/037 ,  G11C7/22 ,  G11C11/417 ,  G11C11/412

    摘要： A clock circuit includes a latch circuit, a memory state latch circuit, a memory state trigger circuit and a clock trigger circuit. The latch circuit is configured to latch an enable signal, and to generate a latch output signal based on a first clock signal or an output clock signal. The memory state latch circuit is configured to generate the output clock signal responsive to a first control signal. The memory state trigger circuit is coupled to the memory state latch circuit, and configured to adjust the output clock signal responsive to the latch output signal. The clock trigger circuit is coupled to the latch circuit or the memory state trigger circuit by a first node, configured to generate the first clock signal responsive to a second clock signal, and configured to control the latch circuit and the memory state trigger circuit based on the first clock signal.

    Clock circuit and method of operating the same
    10.
    发明授权
    Clock circuit and method of operating the same 有权

    公开(公告)号：US10574213B2

    公开(公告)日：2020-02-25

    申请号：US16207064

    申请日：2018-11-30

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Hao-I Yang ,  Cheng Hung Lee ,  Chen-Lin Yang ,  Chiting Cheng ,  Fu-An Wu ,  Yangsyu Lin

    IPC分类号： H03K3/037 ,  G11C11/412 ,  G06F1/04 ,  G11C7/22 ,  G11C11/417

    摘要： A clock circuit includes a first latch circuit, second latch circuit, first trigger circuit and second trigger circuit. The first latch circuit is configured to generate a first latch output signal based on at least a trigger signal or an output clock signal. The second latch circuit is coupled to the first latch circuit, and configured to generate the output clock signal responsive to a control signal. The first trigger circuit is coupled to the second latch circuit, and configured to adjust the output clock signal responsive to at least the first latch output signal. The second trigger circuit is coupled to the first latch circuit and the first trigger circuit by a first node, configured to generate the trigger signal responsive to an input clock signal, and configured to control the first latch circuit and the first trigger circuit based on at least the trigger signal.