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17 条记录 (耗时 0.019 秒)

    COMPRESSOR CIRCUIT AND COMPRESSOR CIRCUIT LAYOUT
    1.
    发明申请
    COMPRESSOR CIRCUIT AND COMPRESSOR CIRCUIT LAYOUT 有权
    压缩机电路和压缩机电路布局

    公开(公告)号：US20160156358A1

    公开(公告)日：2016-06-02

    申请号：US14740499

    申请日：2015-06-16

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Chi-Lin LIU ,  Lee-Chung LU ,  Meng-Hsueh WANG ,  Shang-Chih HSIEH ,  Henry HUANG ,  Ji-Yung LIN

    IPC分类号： H03K19/21

    CPC分类号： H03K19/21

    摘要： A compressor circuit includes a plurality of inputs, a sum output, and a plurality of XOR circuits. Each XOR circuit of the plurality of XOR circuits includes first, second and third inputs, and a first output. The XOR circuit is configured to generate a logic value A⊕B⊕C at the first output, where A, B and C are logic values at the corresponding first, second and third inputs, and “⊕” is the XOR logic operation. The plurality of XOR circuits includes first and second XOR circuits. The first, second and third inputs of the first XOR circuit are coupled to corresponding inputs among the plurality of inputs of the compressor circuit. The first output of the first XOR circuit is coupled to the first input of the second XOR circuit. The first output of the second XOR circuit is coupled to the sum output.

    摘要翻译： 压缩机电路包括多个输入，和输出和多个异或电路。 多个XOR电路的每个XOR电路包括第一，第二和第三输入以及第一输出。 XOR电路被配置为在第一输出处产生逻辑值A⊕B⊕C，其中A，B和C是对应的第一，第二和第三输入端的逻辑值，“⊕”是异或逻辑运算。 多个异或电路包括第一和第二异或电路。 第一异或电路的第一，第二和第三输入端耦合到压缩机电路的多个输入端之间的相应输入端。 第一异或电路的第一输出耦合到第二异或电路的第一输入端。 第二异或电路的第一输出耦合到和输出。

    CLOCK GATING CIRCUIT AND METHOD OF OPERATING THE SAME
    2.
    发明申请
    CLOCK GATING CIRCUIT AND METHOD OF OPERATING THE SAME 有权

    公开(公告)号：US20230110352A1

    公开(公告)日：2023-04-13

    申请号：US18065327

    申请日：2022-12-13

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Seid Hadi RASOULI ,  Jerry Chang Jui KAO ,  Xiangdong CHEN ,  Tzu-Ying LIN ,  Yung-Chen CHEN ,  Hui-Zhong ZHUANG ,  Chi-Lin LIU

    IPC分类号： H03K3/037 ,  H03K19/20 ,  G06F1/12

    摘要： A clock gating circuit includes a NOR logic gate, a transmission gate, a cross-coupled pair of transistors, and a first transistor. The NOR logic gate is coupled to a first node, and receives a first and a second enable signal, and outputs a first control signal. The transmission gate is coupled between the first and a second node, and receives the first control signal, an inverted clock input signal and a clock output signal. The cross-coupled pair of transistors is coupled between the second node and an output node, and receives at least a second control signal. The first transistor includes a first gate terminal configured to receive the inverted clock input signal, a first drain terminal coupled to the output node, and a first source terminal coupled to a reference voltage supply. The first transistor adjusts the clock output signal responsive to the inverted clock input signal.

    CLOCK GATING CIRCUIT AND METHOD OF OPERATING THE SAME
    5.
    发明申请
    CLOCK GATING CIRCUIT AND METHOD OF OPERATING THE SAME 有权

    公开(公告)号：US20210226615A1

    公开(公告)日：2021-07-22

    申请号：US17095191

    申请日：2020-11-11

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Hadi RASOULI ,  Jerry Chang Jui KAO ,  Xiangdong CHEN ,  Tzu-Ying LIN ,  Yung-Chen CHEN ,  Hui-Zhong ZHUANG ,  Chi-Lin LIU

    IPC分类号： H03K3/037 ,  H03K19/20 ,  G06F1/12

    摘要： A clock gating circuit includes a NOR logic gate, a transmission gate, a cross-coupled pair of transistors, and a first transistor. The NOR logic gate is coupled to a first node, and receives a first and a second enable signal, and outputs a first control signal. The transmission gate is coupled between the first and a second node, and receives the first control signal, an inverted clock input signal and a clock output signal. The cross-coupled pair of transistors is coupled between the second node and an output node, and receives at least a second control signal. The first transistor includes a first gate terminal configured to receive the inverted clock input signal, a first drain terminal coupled to the output node, and a first source terminal coupled to a reference voltage supply. The first transistor adjusts the clock output signal responsive to the inverted clock input signal.

    METHOD AND SYSTEM OF EXPANDING SET OF STANDARD CELLS WHICH COMPRISE A LIBRARY
    6.
    发明申请
    METHOD AND SYSTEM OF EXPANDING SET OF STANDARD CELLS WHICH COMPRISE A LIBRARY 审中-公开

    公开(公告)号：US20200272778A1

    公开(公告)日：2020-08-27

    申请号：US15930010

    申请日：2020-05-12

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Chi-Lin LIU ,  Sheng-Hsiung CHEN ,  Jerry Chang-Jui KAO ,  Fong-Yuan CHANG ,  Lee-Chung LU ,  Shang-Chih HSIEH ,  Wei-Hsiang MA

    IPC分类号： G06F30/327

    摘要： A method includes: identifying ad hoc groups of elementary standard cells recurrent in a layout diagram, selecting one of the recurrent ad hoc groups (selected group) such that: the elementary standard cells in the selected group have connections representing a corresponding logic circuit; each elementary standard cell representing a logic gate; each ad hoc group has a number of transistors and a first number of logic gates; and the selected group providing a logical function. The method includes generating one or more macro standard cells such that: each macro standard cell has a number of transistors which is smaller than the number of transistors of the corresponding ad hoc group; or each macro standard cell has a second number of logic gates different than the first number of logic gates of the corresponding ad hoc group. The method also includes adding macro standard cells to the set of standard cells.

    FLIP FLOP CIRCUIT AND METHOD OF OPERATING THE SAME
    7.
    发明申请
    FLIP FLOP CIRCUIT AND METHOD OF OPERATING THE SAME 审中-公开

    公开(公告)号：US20170170811A1

    公开(公告)日：2017-06-15

    申请号：US15443504

    申请日：2017-02-27

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Chi-Lin LIU ,  Shang-Chih HSIEH ,  Lee-Chung LU ,  Chang-Yu WU

    IPC分类号： H03K3/356 ,  H03K3/037

    CPC分类号： H03K3/356104 ,  G01R31/318541 ,  H03K3/037 ,  H03K3/356121

    摘要： A flip-flop circuit includes a first latch, a second latch and a trigger circuit. The first latch is configured to set a first output signal based on a first input signal and a clock signal. The second latch is configured to set a second output signal based on a second input signal and the clock signal. The trigger circuit is coupled with the first latch and the second latch. The trigger circuit is configured to generate the second input signal based on at least the second output signal. The trigger circuit is configured to cause the second input signal to have different voltage swings based on the first output signal and the second output signal. The trigger circuit includes a logic circuit coupled to at least the first latch or the second latch. The logic circuit is configured to output the second output signal.

    LOGIC CIRCUITS WITH REDUCED TRANSISTOR COUNTS
    8.
    发明公开
    LOGIC CIRCUITS WITH REDUCED TRANSISTOR COUNTS 审中-公开

    公开(公告)号：US20230376661A1

    公开(公告)日：2023-11-23

    申请号：US18362938

    申请日：2023-07-31

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Chi-Lin LIU ,  Jerry Chang-Jui KAO ,  Wei-Hsiang MA ,  Lee-Chung LU ,  Fong-Yuan CHANG ,  Sheng-Hsiung CHEN ,  Shang-Chih HSIEH

    IPC分类号： G06F30/327

    CPC分类号： G06F30/327 ,  G06F2111/06

    摘要： A logic circuit (for providing a multibit flip-flop (MBFF) function) includes: a first inverter to receive a clock signal and generate a corresponding clock_bar signal; a second inverter to receive the clock_bar signal and generate a corresponding clock_bar_bar signal; a third inverter to receive a control signal and generate a corresponding control_bar signal; and a series-chain of 1-bit transfer flip-flop (TXFF) circuits, each including: a NAND circuit to receive data signals; and a 1-bit transmit gate flip-flop (TGFF) circuit to output signals Q and q, and receive an output of the NAND circuit, the signal q from the TGFF circuit of a preceding TXFF circuit in the series-chain, the clock_bar and clock_bar_bar signals, and the control and control_bar signals; and the first transfer TXFF circuit in the series-chain being configured to receive a start signal in place of the signal q from an otherwise preceding TGFF circuit.