公开(公告)号：US20220352151A1

公开(公告)日：2022-11-03

申请号：US17864383

申请日：2022-07-13

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Harry Hak-Lay CHUANG ,  Wei Cheng WU

IPC分类号： H01L27/088 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/161 ,  H01L29/16 ,  H01L21/265 ,  H01L21/266 ,  H01L29/66 ,  H01L21/02 ,  H01L29/165 ,  H01L27/092

摘要： A method of fabricating a semiconductor device includes forming first gate structure and a second gate structure over a core device region of a substrate. The method further includes forming stressors at opposite sides of the first gate structure. The method further includes doping the stressors to form a first source region and a first drain region of a first device. The method further includes doping into the substrate and at opposite sides of the second gate structure to form a second source region and a second drain region of a second device, wherein the first source region, the first drain region, the second source region and the second drain region are of a same conductivity, and the first source region comprises a different material from the second source region.

公开(公告)号：US20150228645A1

公开(公告)日：2015-08-13

申请号：US14178429

申请日：2014-02-12

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Harry Hak-Lay CHUANG ,  Wei Cheng WU

IPC分类号： H01L27/088 ,  H01L29/78 ,  H01L29/161 ,  H01L21/02 ,  H01L21/265 ,  H01L21/266 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/16

CPC分类号： H01L27/088 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/26513 ,  H01L21/2652 ,  H01L21/266 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823462 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/51 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

摘要： A semiconductor device includes a semiconductor substrate, and first and second transistors over the semiconductor substrate. Both the first and second transistors are p-type transistors or both the first and second transistors are n-type transistors. The first and second transistors have the same nominal operating voltage. The first transistor has a higher threshold voltage than the second transistor. The second transistor has at least one of a source region or a drain region with higher charge carrier mobility than at least one of a source region or a drain region of the first transistor.

摘要翻译： 半导体器件包括半导体衬底，以及半导体衬底上的第一和第二晶体管。 第一和第二晶体管都是p型晶体管，或者第一和第二晶体管都是n型晶体管。 第一和第二晶体管具有相同的标称工作电压。 第一晶体管具有比第二晶体管更高的阈值电压。 第二晶体管具有比第一晶体管的源极区域或漏极区域中的至少一个更高的电荷载流子迁移率的源极区域或漏极区域中的至少一个。

公开(公告)号：US20160372462A1

公开(公告)日：2016-12-22

申请号：US15192706

申请日：2016-06-24

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Po-Nien CHEN ,  Bao-Ru YOUNG ,  Chi-Hsun HSIEH ,  Harry Hak-Lay CHUANG ,  Wei Cheng WU ,  Eric HUANG

IPC分类号： H01L27/088 ,  H01L29/51 ,  H01L29/40 ,  H01L21/28 ,  H01L21/8234

CPC分类号： H01L27/088 ,  H01L21/28158 ,  H01L21/823462 ,  H01L21/82385 ,  H01L21/823857 ,  H01L29/511 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

摘要： An exemplary integrated circuit comprises: a first device gate disposed over the first device region, the first device gate comprising a first interfacial layer and a first dielectric layer; a second device gate disposed over the second device region, the second device gate comprising a second interfacial layer and a second dielectric layer; and a third device gate disposed over the third device region, the third device gate comprising a third interfacial layer and a third dielectric layer, wherein the first interfacial layer, the second interfacial layer, and the third interfacial layer are different from each other in at least one of a thickness and an interfacial material.

摘要翻译： 示例性集成电路包括：设置在第一器件区域上的第一器件栅极，第一器件栅极包括第一界面层和第一介电层; 设置在所述第二器件区域上的第二器件栅极，所述第二器件栅极包括第二界面层和第二介电层; 以及设置在所述第三器件区域上的第三器件栅极，所述第三器件栅极包括第三界面层和第三介电层，其中所述第一界面层，所述第二界面层和所述第三界面层在第 至少一种厚度和界面材料。

公开(公告)号：US20200168603A1

公开(公告)日：2020-05-28

申请号：US16779143

申请日：2020-01-31

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Harry Hak-Lay CHUANG ,  Wei Cheng WU

IPC分类号： H01L27/088 ,  H01L29/165 ,  H01L21/265 ,  H01L21/8234 ,  H01L21/02 ,  H01L29/66 ,  H01L21/266 ,  H01L29/16 ,  H01L29/161 ,  H01L29/78

摘要： A method of fabricating a semiconductor device includes forming first gate structure and a second gate structure over a core device region of a substrate. The method further includes forming stressors at opposite sides of the first gate structure. The method further includes doping the stressors to form a first source region and a first drain region of a first device. The method further includes doping into the substrate and at opposite sides of the second gate structure to form a second source region and a second drain region of a second device, wherein the first source region, the first drain region, the second source region and the second drain region are of a same conductivity, and the first source region comprises a different material from the second source region.

公开(公告)号：US20230380155A1

公开(公告)日：2023-11-23

申请号：US18231427

申请日：2023-08-08

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Wei Cheng WU ,  Li-Feng TENG

IPC分类号： H10B41/42 ,  H01L29/423 ,  H01L21/28 ,  H10B41/30 ,  H10B41/35 ,  H10B41/44 ,  H10B41/47 ,  H10B41/48 ,  H10B43/30 ,  H01L29/66

CPC分类号： H10B41/42 ,  H01L29/42344 ,  H01L29/40114 ,  H10B41/30 ,  H10B41/35 ,  H10B41/44 ,  H10B41/47 ,  H10B41/48 ,  H10B43/30 ,  H01L29/42328 ,  H01L29/66545

摘要： A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate and a second dielectric layer disposed between the floating gate and the control gate. The second dielectric layer includes one of a silicon oxide layer, a silicon nitride layer and a multi-layer thereof. The first dielectric layer includes a first-first dielectric layer formed on the substrate and a second-first dielectric layer formed on the first-first dielectric layer. The second-first dielectric layer includes a dielectric material having a dielectric constant higher than silicon nitride.

公开(公告)号：US20220359552A1

公开(公告)日：2022-11-10

申请号：US17874280

申请日：2022-07-26

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chen-Chin LIU ,  Wei Cheng WU ,  Yi Hsien LU ,  Yu-Hsiung WANG ,  Juo-Li YANG

IPC分类号： H01L27/11546 ,  H01L27/088 ,  H01L29/788 ,  H01L21/28 ,  H01L27/105 ,  H01L27/11 ,  G11C16/12 ,  G11C16/04 ,  H01L27/092 ,  H01L21/8238 ,  H01L27/11548 ,  H01L27/11531 ,  H01L29/423

摘要： In a method of manufacturing a semiconductor device, a memory cell structure covered by a protective layer is formed in a memory cell area of a substrate. A mask pattern is formed. The mask pattern has an opening over a first circuit area, while the memory cell area and a second circuit area are covered by the mask pattern. The substrate in the first circuit area is recessed, while the memory cell area and the second circuit area are protected. A first field effect transistor (FET) having a first gate dielectric layer is formed in the first circuit area over the recessed substrate and a second FET having a second gate dielectric layer is formed in the second circuit area over the substrate as viewed in cross section.

公开(公告)号：US20170323886A1

公开(公告)日：2017-11-09

申请号：US15662541

申请日：2017-07-28

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Harry Hak-Lay CHUANG ,  Wei Cheng WU

IPC分类号： H01L27/088 ,  H01L21/8234 ,  H01L21/02 ,  H01L29/66 ,  H01L29/165 ,  H01L29/161 ,  H01L29/16 ,  H01L21/266 ,  H01L21/265 ,  H01L29/78 ,  H01L29/51

CPC分类号： H01L27/088 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/26513 ,  H01L21/2652 ,  H01L21/266 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823462 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/51 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

摘要： A method of fabricating a semiconductor device includes forming first gate structure and a second gate structure over a core device region of a substrate. The method further includes forming stressors at opposite sides of the first gate structure. The method further includes doping the stressors to form a first source region and a first drain region of a first device. The method further includes doping into the substrate and at opposite sides of the second gate structure to form a second source region and a second drain region of a second device, wherein the first source region, the first drain region, the second source region and the second drain region are of a same conductivity. The first source region includes a different material from the second source region.