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公开(公告)号:US10283210B2
公开(公告)日:2019-05-07
申请号:US16133783
申请日:2018-09-18
发明人: Yu-Der Chih , Chen-Ming Hung , Jen-Chou Tseng , Jam-Wem Lee , Ming-Hsiang Song , Shu-Chuan Lee , Shao-Yu Chou , Yu-Ti Su
摘要: A memory device includes a memory circuit and a fuse protection circuit. The memory circuit includes a memory cell and a program line. The memory cell includes a fuse. The program line is configured to receive a program voltage for programming the fuse. The fuse protection circuit is coupled to the memory circuit and is configured to prevent unintentional programming of the fuse.
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公开(公告)号:US20150129971A1
公开(公告)日:2015-05-14
申请号:US14079744
申请日:2013-11-14
发明人: Ming-Hsiang Song , Jam-Wem Lee , Yi-Feng Chang , Wun-Jie Hung Lin
IPC分类号: H01L27/088 , H01L29/66
CPC分类号: H01L27/0251 , H01L21/26513 , H01L21/823437 , H01L21/823493 , H01L21/823828 , H01L21/823871 , H01L21/823892 , H01L27/0207 , H01L27/088 , H01L27/0928 , H01L29/66477
摘要: A semiconductor arrangement includes a well region and a first region disposed within the well region. The first region includes a first conductivity type. The semiconductor arrangement includes a first gate disposed above the well region on a first side of the first region. The first gate includes a first top surface facing away from the well region. The first top surface has a first top surface area. The semiconductor arrangement includes a first gate contact disposed above the first gate. The first gate contact includes a first bottom surface facing towards the well region. The first bottom surface has a first bottom surface area. The first bottom surface area covers at least about two thirds of the first top surface area.
摘要翻译: 半导体装置包括阱区和设置在阱区内的第一区。 第一区域包括第一导电类型。 半导体装置包括设置在第一区域的第一侧上的阱区上方的第一栅极。 第一门包括面向远离井区的第一顶面。 第一顶表面具有第一顶表面区域。 半导体装置包括设置在第一栅极上方的第一栅极触点。 第一门接触包括面向井区域的第一底面。 第一底表面具有第一底表面区域。 第一底表面区域覆盖第一顶表面区域的至少约三分之二。
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公开(公告)号:US10109366B2
公开(公告)日:2018-10-23
申请号:US15493964
申请日:2017-04-21
发明人: Yu-Der Chih , Chen-Ming Hung , Jen-Chou Tseng , Jam-Wem Lee , Ming-Hsiang Song , Shu-Chuan Lee , Shao-Yu Chou , Yu-Ti Su
摘要: A memory device includes a memory circuit and a fuse protection circuit. The memory circuit includes a memory cell and a program line. The memory cell includes a fuse. The program line is configured to receive a program voltage for programming the fuse. The fuse protection circuit is coupled to the memory circuit and is configured to prevent unintentional programming of the fuse.
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公开(公告)号:US20200227126A1
公开(公告)日:2020-07-16
申请号:US16830429
申请日:2020-03-26
发明人: Yu-Der Chih , Chen-Ming Hung , Jen-Chou Tseng , Jam-Wem Lee , Ming-Hsiang Song , Shu-Chuan Lee , Shao-Yu Chou , Yu-Ti Su
摘要: A memory device includes a memory circuit and a fuse protection circuit. The memory circuit includes a program line and a fuse. The program line is configured to receive a program voltage for programming the fuse. The fuse protection circuit is coupled to the memory circuit and is configured to prevent unintentional programming of the fuse.
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公开(公告)号:US09978739B2
公开(公告)日:2018-05-22
申请号:US15603516
申请日:2017-05-24
发明人: Ming-Hsiang Song , Jam-Wem Lee , Yi-Feng Chang , Wun-Jie Lin
IPC分类号: H01L27/02 , H01L27/092 , H01L27/088 , H01L21/8238 , H01L29/66 , H01L21/8234 , H01L21/265
CPC分类号: H01L27/0251 , H01L21/26513 , H01L21/823437 , H01L21/823493 , H01L21/823828 , H01L21/823871 , H01L21/823892 , H01L27/0207 , H01L27/088 , H01L27/0928 , H01L29/66477
摘要: A semiconductor arrangement includes a well region and a first region disposed within the well region. The first region includes a first conductivity type. The semiconductor arrangement includes a first gate disposed above the well region on a first side of the first region. The first gate includes a first top surface facing away from the well region. The first top surface has a first top surface area. The semiconductor arrangement includes a first gate contact disposed above the first gate. The first gate contact includes a first bottom surface facing towards the well region. The first bottom surface has a first bottom surface area. The first bottom surface area covers at least about two thirds of the first top surface area.
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公开(公告)号:US09666575B2
公开(公告)日:2017-05-30
申请号:US14983641
申请日:2015-12-30
发明人: Ming-Hsiang Song , Jam-Wem Lee , Yi-Feng Chang , Wun-Jie Lin
IPC分类号: H01L27/02 , H01L27/088 , H01L29/66 , H01L21/8234 , H01L21/265 , H01L21/8238 , H01L27/092
CPC分类号: H01L27/0251 , H01L21/26513 , H01L21/823437 , H01L21/823493 , H01L21/823828 , H01L21/823871 , H01L21/823892 , H01L27/0207 , H01L27/088 , H01L27/0928 , H01L29/66477
摘要: A semiconductor arrangement includes a well region and a first region disposed within the well region. The first region includes a first conductivity type. The semiconductor arrangement includes a first gate disposed above the well region on a first side of the first region. The first gate includes a first top surface facing away from the well region. The first top surface has a first top surface area. The semiconductor arrangement includes a first gate contact disposed above the first gate. The first gate contact includes a first bottom surface facing towards the well region. The first bottom surface has a first bottom surface area. The first bottom surface area covers at least about two thirds of the first top surface area.
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公开(公告)号:US20160133619A1
公开(公告)日:2016-05-12
申请号:US14983641
申请日:2015-12-30
发明人: Ming-Hsiang Song , Jam-Wem Lee , Yi-Feng Chang , Wun-Jie Lin
IPC分类号: H01L27/02 , H01L21/8238 , H01L21/265 , H01L27/092
CPC分类号: H01L27/0251 , H01L21/26513 , H01L21/823437 , H01L21/823493 , H01L21/823828 , H01L21/823871 , H01L21/823892 , H01L27/0207 , H01L27/088 , H01L27/0928 , H01L29/66477
摘要: A semiconductor arrangement includes a well region and a first region disposed within the well region. The first region includes a first conductivity type. The semiconductor arrangement includes a first gate disposed above the well region on a first side of the first region. The first gate includes a first top surface facing away from the well region. The first top surface has a first top surface area. The semiconductor arrangement includes a first gate contact disposed above the first gate. The first gate contact includes a first bottom surface facing towards the well region. The first bottom surface has a first bottom surface area. The first bottom surface area covers at least about two thirds of the first top surface area.
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公开(公告)号:US09230961B2
公开(公告)日:2016-01-05
申请号:US14079744
申请日:2013-11-14
发明人: Ming-Hsiang Song , Jam-Wem Lee , Yi-Feng Chang , Wun-Jie Hung Lin
IPC分类号: H01L29/06 , H01L31/00 , H01L23/52 , H01L29/80 , H01L29/66 , H01L21/70 , H01L27/088 , H01L23/48 , H01L21/8234 , H01L27/02
CPC分类号: H01L27/0251 , H01L21/26513 , H01L21/823437 , H01L21/823493 , H01L21/823828 , H01L21/823871 , H01L21/823892 , H01L27/0207 , H01L27/088 , H01L27/0928 , H01L29/66477
摘要: A semiconductor arrangement includes a well region and a first region disposed within the well region. The first region includes a first conductivity type. The semiconductor arrangement includes a first gate disposed above the well region on a first side of the first region. The first gate includes a first top surface facing away from the well region. The first top surface has a first top surface area. The semiconductor arrangement includes a first gate contact disposed above the first gate. The first gate contact includes a first bottom surface facing towards the well region. The first bottom surface has a first bottom surface area. The first bottom surface area covers at least about two thirds of the first top surface area.
摘要翻译: 半导体装置包括阱区和设置在阱区内的第一区。 第一区域包括第一导电类型。 半导体装置包括设置在第一区域的第一侧上的阱区上方的第一栅极。 第一门包括面向远离井区的第一顶面。 第一顶表面具有第一顶表面区域。 半导体装置包括设置在第一栅极上方的第一栅极触点。 第一门接触包括面向井区域的第一底面。 第一底表面具有第一底表面区域。 第一底表面区域覆盖第一顶表面区域的至少约三分之二。
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公开(公告)号:US10991442B2
公开(公告)日:2021-04-27
申请号:US17013967
申请日:2020-09-08
发明人: Yu-Der Chih , Chen-Ming Hung , Jen-Chou Tseng , Jam-Wem Lee , Ming-Hsiang Song , Shu-Chuan Lee , Shao-Yu Chou , Yu-Ti Su
摘要: A memory device includes a memory circuit and a fuse protection circuit. The memory circuit includes a program line and a fuse. The program line is configured to receive a program voltage for programming the fuse. The fuse protection circuit is coupled to the memory circuit and is configured to prevent unintentional programming of the fuse.
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公开(公告)号:US10803967B2
公开(公告)日:2020-10-13
申请号:US16830429
申请日:2020-03-26
发明人: Yu-Der Chih , Chen-Ming Hung , Jen-Chou Tseng , Jam-Wem Lee , Ming-Hsiang Song , Shu-Chuan Lee , Shao-Yu Chou , Yu-Ti Su
摘要: A memory device includes a memory circuit and a fuse protection circuit. The memory circuit includes a program line and a fuse. The program line is configured to receive a program voltage for programming the fuse. The fuse protection circuit is coupled to the memory circuit and is configured to prevent unintentional programming of the fuse.
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