公开(公告)号：US20170207299A1

公开(公告)日：2017-07-20

申请号：US15137553

申请日：2016-04-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： HSING-LIEN LIN ,  HAI-DANG TRINH ,  CHENG-YUAN TSAI

IPC: H01L49/02 ,  H01L21/02 ,  H01L21/8256 ,  H01L21/3213 ,  H01L21/768

CPC classification number: H01L28/60 ,  H01L21/76895 ,  H01L21/8256

Abstract: A method of forming a metal-insulator-metal capacitor is provided. The method includes forming a first metal plate over a semiconductor substrate, forming a first dielectric layer with a first dielectric constant on a surface of the first metal plate, forming a second dielectric layer with a second dielectric constant on a surface of the first dielectric layer, forming a third dielectric layer with a third dielectric constant on a surface of the second dielectric layer, and forming a second metal plate on a surface of the third dielectric layer. The second dielectric constant is different from the first dielectric constant and different from the third dielectric constant.

公开(公告)号：US20170313574A1

公开(公告)日：2017-11-02

申请号：US15142806

申请日：2016-04-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： YUAN-CHIH HSIEH ,  HSING-LIEN LIN ,  JUNG-HUEI PENG ,  YI-CHIEN WU

IPC: B81B3/00 ,  B81C1/00

CPC classification number: B81B3/0005 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81B2203/04

Abstract: The present disclosure provides a method of manufacturing a structure. The method comprises: providing a first substrate; forming a plurality of conductive pads over the first substrate; forming a film on a first subset of the plurality of conductive pads, thereby leaving a second subset of the plurality of conductive pads exposed from the film; forming a self-assembled monolayer (SAM) over the film; and forming a cavity by the first substrate and a second substrate through bonding a portion of the second substrate to the second subset of the plurality of conductive pads that are exposed from the film.

公开(公告)号：US20250081864A1

公开(公告)日：2025-03-06

申请号：US18950227

申请日：2024-11-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： HAI-DANG TRINH ,  FA-SHEN JIANG ,  HSING-LIEN LIN ,  CHII-MING WU

IPC: H10N70/00

Abstract: A semiconductor device includes a diffusion barrier structure, a bottom electrode, a top electrode, a switching layer and a capping layer. The bottom electrode is over the diffusion barrier structure. The top electrode is over the bottom electrode. The switching layer is between the bottom electrode and the top electrode, and configured to store data. The capping layer is between the switching layer and the top electrode. The diffusion barrier structure includes a multiple-layer structure. A thermal conductivity of the diffusion barrier structure is greater than approximately 20 W/mK.

公开(公告)号：US20210135102A1

公开(公告)日：2021-05-06

申请号：US16844875

申请日：2020-04-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： HSING-LIEN LIN ,  FU-TING SUNG ,  CHING JU YANG ,  CHII-MING WU

IPC: H01L45/00 ,  G11C13/00 ,  H01L27/24

Abstract: A semiconductor memory structure includes a memory cell, an encapsulation layer over a sidewall of the memory cell, and a nucleation layer between the sidewall of the memory cell and the encapsulation layer. The memory cell includes a top electrode, a bottom electrode and a data-storage element sandwiched between the bottom electrode and the top electrode. The nucleation layer includes metal oxide.

公开(公告)号：US20190157551A1

公开(公告)日：2019-05-23

申请号：US16157736

申请日：2018-10-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： HSING-LIEN LIN ,  HAI-DANG TRINH ,  FA-SHEN JIANG

IPC: H01L45/00 ,  H01L27/24

Abstract: A semiconductor structure includes a first conductive layer and a second conductive layer, and a memory device between the first conductive layer and the second conductive layer. The memory device includes a top electrode, a bottom electrode adjacent to the first conductive layer, and a phase change material between the top electrode and the bottom electrode. The bottom electrode includes a first portion and a second portion between the first portion and the first conductive layer.

公开(公告)号：US20230255125A1

公开(公告)日：2023-08-10

申请号：US18302007

申请日：2023-04-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： HSING-LIEN LIN ,  FU-TING SUNG ,  CHING JU YANG ,  CHII-MING WU

IPC: H10N70/00 ,  G11C13/00 ,  H10B63/00 ,  H10N70/20

CPC classification number: H10N70/841 ,  G11C13/0007 ,  H10B63/30 ,  H10N70/253 ,  H10N70/826 ,  H10N70/883

Abstract: A method for forming a semiconductor memory structure include forming a pillar structure. The pillar structure includes a first conductive layer, a second conductive layer and a data storage material layer between the first and second conducive layers. A sidewall of the first conductive layer, a sidewall of the data storage layer and a sidewall of the second conductive layer are exposed. An oxygen-containing plasma treatment is performed on the pillar structure to form hydrophilic surfaces of the sidewall of the first conductive layer, the sidewall of the data storage layer and the sidewall of the second conductive layer. An encapsulation layer is formed over the pillar structure and the dielectric layer. The encapsulation layer is in contact with the hydrophilic surfaces of the sidewall of the first conductive layer, the sidewall of the data storage layer and the sidewall of the second conductive layer.

公开(公告)号：US20220367806A1

公开(公告)日：2022-11-17

申请号：US17839693

申请日：2022-06-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： HAI-DANG TRINH ,  HSING-LIEN LIN ,  FA-SHEN JIANG

IPC: H01L45/00

Abstract: A semiconductor device includes a bottom electrode, a top electrode over the bottom electrode, a switching layer between the bottom electrode and the top electrode, wherein the switching layer is configured to store data, a capping layer in contact with the switching layer, wherein the capping layer is configured to extract active metal ions from the switching layer, an ion reservoir region formed in the capping layer, a diffusion barrier layer between the bottom electrode and the switching layer, wherein the diffusion barrier layer includes palladium (Pd), cobalt (Co), or a combination thereof and is configured to obstruct diffusion of the active metal ions between the switching layer and the bottom electrode, and the diffusion layer has a concaved top surface, and a passivation layer covering a portion of the top electrode, and wherein the passivation layer directly contacts a top surface of the switching layer.

公开(公告)号：US20200052203A1

公开(公告)日：2020-02-13

申请号：US16657797

申请日：2019-10-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： HAI-DANG TRINH ,  FA-SHEN JIANG ,  HSING-LIEN LIN ,  CHII-MING WU

IPC: H01L45/00

Abstract: A semiconductor device includes a diffusion barrier structure, a bottom electrode, a top electrode over the bottom electrode, a switching layer and a capping layer. The bottom electrode is over the diffusion barrier structure. The top electrode is over the bottom electrode. The switching layer is between the bottom electrode and the top electrode, and configured to store data. The capping layer is between the top electrode and the switching layer. A thermal conductivity of the diffusion barrier structure is greater than approximately 20 W/mK.

公开(公告)号：US20230062897A1

公开(公告)日：2023-03-02

申请号：US18046924

申请日：2022-10-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： HAI-DANG TRINH ,  FA-SHEN JIANG ,  HSING-LIEN LIN ,  CHII-MING WU

IPC: H01L45/00

Abstract: A semiconductor device includes a diffusion barrier structure, a bottom electrode, a top electrode, a switching layer and a capping layer. The bottom electrode is over the diffusion barrier structure. The top electrode is over the bottom electrode. The switching layer is between the bottom electrode and the top electrode, and configured to store data. The capping layer is between the switching layer and the top electrode. The diffusion barrier structure includes a multiple-layer structure. A thermal conductivity of the diffusion barrier structure is greater than approximately 20 W/mK.

公开(公告)号：US20210288248A1

公开(公告)日：2021-09-16

申请号：US17335831

申请日：2021-06-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： HSING-LIEN LIN ,  HAI-DANG TRINH ,  FA-SHEN JIANG

IPC: H01L45/00

Abstract: A method for forming a semiconductor structure includes following operations. A first conductive layer is formed. A first dielectric layer is formed over the first conductive layer, and the first dielectric layer includes at least one trench exposing the first conductive layer. A second conductive layer is formed in the trench. A third conductive layer is formed in the trench, and a resistivity of the third conductive layer is greater than a resistivity of the second conductive layer. A second dielectric layer is formed over the third conductive layer. A phase change material is formed over the first dielectric layer.