Semiconductor device and manufacturing method thereof
    4.
    发明授权
    Semiconductor device and manufacturing method thereof 有权
    半导体装置及其制造方法

    公开(公告)号:US09422151B1

    公开(公告)日:2016-08-23

    申请号:US14858414

    申请日:2015-09-18

    IPC分类号: B81B3/00 B81C1/00

    CPC分类号: B81B3/0013 B81B2203/0127

    摘要: A semiconductor device includes a substrate and a movable membrane proximal to the substrate. The semiconductor device further includes a mesa over the substrate and protruded from a surface of the substrate toward the movable membrane. The mesa includes a strike hitting portion configured to receive a striking force from the membrane and a hybrid stress buffer under the strike hitting portion, wherein the hybrid stress buffer includes at least two layers which are distinguishable by a difference in hardness.

    摘要翻译: 半导体器件包括基板和靠近基板的可动膜。 半导体器件还包括在衬底上的台面并从衬底的表面向可移动膜突出。 台面包括构造成接收来自膜的打击力的击打部分和在击打部分下方的混合应力缓冲器,其中混合应力缓冲器包括可由硬度差异区分的至少两层。

    Bond Wave Optimization Method and Device
    6.
    发明公开

    公开(公告)号:US20230382723A1

    公开(公告)日:2023-11-30

    申请号:US18231904

    申请日:2023-08-09

    IPC分类号: B81C1/00 B81B7/00

    CPC分类号: B81C1/00333 B81B7/0077

    摘要: A semiconductor device and method of manufacturing the device that includes a growth die and a dummy die. The method includes patterning, on an integrated circuit wafer, at one least growth die, and patterning at least one dummy die that is positioned on at least a portion of a circumference of the integrated circuit wafer. The patterned growth and dummy dies are etched on the wafer. A bond wave is initiated at a starting point on the integrated circuit wafer. The starting point is positioned on an edge of the integrated circuit wafer opposite the portion on which the at least one dummy die is patterned. Upon application of pressure at the starting point, a uniform bond wave propagates across the wafers, bonding the two wafers together.

    MEMS device
    7.
    发明授权

    公开(公告)号:US11220422B2

    公开(公告)日:2022-01-11

    申请号:US16353484

    申请日:2019-03-14

    IPC分类号: B81B3/00 G01C19/5656

    摘要: A micro-electro-mechanical system (MEMS) device includes a substrate, a proof mass, and a piezoelectric bump. The substrate has a surface. The proof mass is suspended over the surface of the substrate, wherein the proof mass is movable with respect to the substrate. The piezoelectric bump is disposed on the surface of the substrate and extends a distance from the surface of the substrate toward the proof mass.

    DIELECTRIC PROTECTION LAYER CONFIGURED TO INCREASE PERFORMANCE OF MEMS DEVICE

    公开(公告)号:US20230382724A1

    公开(公告)日:2023-11-30

    申请号:US17825225

    申请日:2022-05-26

    IPC分类号: B81C1/00 B81B3/00

    摘要: Various embodiments of the present disclosure are directed towards an integrated chip including an interconnect structure overlying a semiconductor substrate. An upper dielectric structure overlies the interconnect structure. A microelectromechanical system (MEMS) substrate overlies the upper dielectric structure. A cavity is defined between the MEMS substrate and the upper dielectric structure. The MEMS substrate comprises a movable membrane over the cavity. A cavity electrode is disposed in the upper dielectric structure and underlies the cavity. A plurality of stopper structures is disposed in the cavity between the movable membrane and the cavity electrode. A dielectric protection layer is disposed along a top surface of the cavity electrode. The dielectric protection layer has a greater dielectric constant than the upper dielectric structure.