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公开(公告)号：US20230251306A1
公开(公告)日：2023-08-10
申请号：US18301274
申请日：2023-04-17
发明人： JUN HE , YU-TING LIN , WEI-HSUN LIN , YUNG-LIANG KUO , YINLUNG LU
IPC分类号： G01R31/28
CPC分类号： G01R31/2879 , G01R31/2886
摘要： The present disclosure provides a method and a system for testing semiconductor device. The method includes the following operations. A wafer having an IC formed thereon is provided. The IC is energized by raising the voltage of the IC to a first voltage level during a first period. A stress signal is applied to the IC. The stress signal includes a plurality of sequences during a second period subsequent to the first period. Each of the sequence has a ramp-up stage and a ramp-down stage. The stress signal causes the voltage of the IC to fluctuate between a second voltage level and a third voltage level. Whether the IC complies with a test criterion is determined after applying the stress signal.
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公开(公告)号：US20230345622A1
公开(公告)日：2023-10-26
申请号：US17728758
申请日：2022-04-25
发明人： CHUN-WEI CHANG , JIAN-HONG LIN , SHU-YUAN KU , WEI-CHENG LIU , YINLUNG LU , JUN HE
CPC分类号： H05K1/0242 , H05K1/0251 , H05K1/116 , H05K3/427 , H05K3/429 , H05K2201/0776
摘要： A package component and forming method thereof are provided. The package component includes a substrate and a conductive layer. The substrate includes a first surface. The conductive layer is disposed over the first surface. The conductive layer includes a first conductive feature and a second conductive feature. The second conductive feature covers a portion of the first conductive feature. A resistance of the second conductive feature is lower than a resistance of the first conductive feature.
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公开(公告)号：US20240361380A1
公开(公告)日：2024-10-31
申请号：US18765343
申请日：2024-07-08
发明人： JUN HE , YU-TING LIN , WEI-HSUN LIN , YUNG-LIANG KUO , YINLUNG LU
CPC分类号： G01R31/2879 , G01R31/2642 , G01R31/2886
摘要： The present disclosure provides a method and a system for testing semiconductor device. The system includes a signal generator and a module. The signal generator is configured to apply an initial signal to an input terminal of a DUT during a first period; and apply a stress signal to the input terminal in a second period. The module is configured to: obtain an output signal in response to the initial signal and the stress signal at an output terminal of the DUT, the output signal in response to the stress signal including a first sequence and a second sequence, each of the first sequence and the second sequence having a ramp-up stage and a ramp-down stage, wherein a duration of the first sequence is longer than that of the second sequence; and compare the output signal with the stress signal.
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公开(公告)号：US20210311110A1
公开(公告)日：2021-10-07
申请号：US17353543
申请日：2021-06-21
发明人： JUN HE , YU-TING LIN , WEI-HSUN LIN , YUNG-LIANG KUO , YINLUNG LU
IPC分类号： G01R31/28
摘要： The present disclosure provides a method and a system for testing semiconductor device. The method includes the following operations. A wafer having an IC formed thereon is provided. The IC is energized by raising the voltage of the IC to a first voltage level during a first period. A stress signal is applied to the IC. The stress signal includes a plurality of sequences during a second period subsequent to the first period. Each of the sequence has a ramp-up stage and a ramp-down stage. The stress signal causes the voltage of the IC to fluctuate between a second voltage level and a third voltage level. Whether the IC complies with a test criterion is determined after applying the stress signal.
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公开(公告)号：US20240310434A1
公开(公告)日：2024-09-19
申请号：US18672047
申请日：2024-05-23
发明人： JUN HE , YU-TING LIN , WEI-HSUN LIN , YUNG-LIANG KUO , YINLUNG LU
IPC分类号： G01R31/28
CPC分类号： G01R31/2879 , G01R31/2886
摘要： The present disclosure provides a method and a system for testing semiconductor device. The method includes the following operations: energizing an integrated circuit (IC) on a wafer by raising a voltage of the IC to a first voltage level during a first period, and applying to the IC a stress signal including a first sequence and a second sequence during a second period subsequent to the first period, each of the first sequence and the second sequence having a ramp-up stage and a ramp-down stage. The stress signal causes the voltage of the IC to fluctuate between a second voltage level and a third voltage level, wherein a duration of the first sequence is longer than that of the second sequence.
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公开(公告)号：US20220326300A1
公开(公告)日：2022-10-13
申请号：US17809577
申请日：2022-06-29
发明人： JUN HE , YU-TING LIN , WEI-HSUN LIN , YUNG-LIANG KUO , YINLUNG LU
摘要： The present disclosure provides a method and a system for testing semiconductor device. The method includes providing a device under test (DUT) having an input terminal and an output terminal; applying a voltage having a first voltage level to the input terminal of the DUT during a first period; applying a stress signal to the input terminal of the DUT during a second period subsequent to the first period; obtaining an output signal in response to the stress signal at the output terminal of the DUT; and comparing the output signal with the stress signal. The stress signal includes a plurality of sequences, each having a ramp-up stage and a ramp-down stage. The stress signal has a second voltage level and a third voltage level.
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公开(公告)号：US20220320319A1
公开(公告)日：2022-10-06
申请号：US17398668
申请日：2021-08-10
发明人： MING-TE CHEN , HUI-TING TSAI , JUN HE , KUO-FENG YU , CHUN HSIUNG TSAI
IPC分类号： H01L29/66 , H01L29/78 , H01L27/088 , H01L21/8234 , H01L21/02
摘要： A semiconductor structure, a method for manufacturing a FinFET structure and a method for manufacturing a semiconductor structure are provided. The method for forming a FinFET structure includes: providing a FinFET precursor including a plurality of fins and a plurality of gate trenches between the fins; forming a first portion of the trench dummy of a dummy gate within the plurality of gate trenches; removing at least a part of the first portion of the trench dummy; forming a second portion of the trench dummy over the first portion of the trench dummy; performing a first thermal treatment to the first and second portions of the trench dummy; and forming a blanket dummy of the dummy gate over the second portion of the trench dummy. The present disclosure further provides a FinFET structure with an improved metal gate.
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公开(公告)号：US20210199710A1
公开(公告)日：2021-07-01
申请号：US17198764
申请日：2021-03-11
发明人： JUN HE , YU-TING LIN , WEI-HSUN LIN , YUNG-LIANG KUO , YINLUNG LU
摘要： The present disclosure provides a method and a system for testing semiconductor device. The method includes providing a device under test (DUT) having an input terminal and an output terminal; applying a voltage having a first voltage level to the input terminal of the DUT during a first period; applying a stress signal to the input terminal of the DUT during a second period subsequent to the first period; obtaining an output signal in response to the stress signal at the output terminal of the DUT; and comparing the output signal with the stress signal. The stress signal includes a plurality of sequences, each having a ramp-up stage and a ramp-down stage. The stress signal has a second voltage level and a third voltage level.
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公开(公告)号：US20200064396A1
公开(公告)日：2020-02-27
申请号：US16522551
申请日：2019-07-25
发明人： JUN HE , YU-TING LIN , WEI-HSUN LIN , YUNG-LIANG KUO , YINLUNG LU
IPC分类号： G01R31/28
摘要： The present disclosure provides a method and a system for testing semiconductor device. The method includes the following operations. A wafer having an IC formed thereon is provided. The IC is energized by raising the voltage of the IC to a first voltage level during a first period. A stress signal is applied to the IC. The stress signal includes a plurality of sequences during a second period subsequent to the first period. Each of the sequence has a ramp-up stage and a ramp-down stage. The stress signal causes the voltage of the IC to fluctuate between a second voltage level and a third voltage level. Whether the IC complies with a test criterion is determined after applying the stress signal.
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公开(公告)号：US20240215150A1
公开(公告)日：2024-06-27
申请号：US18423227
申请日：2024-01-25
发明人： CHUN-WEI CHANG , JIAN-HONG LIN , SHU-YUAN KU , WEI-CHENG LIU , YINLUNG LU , JUN HE
CPC分类号： H05K1/0242 , H05K1/0251 , H05K1/116 , H05K3/427 , H05K3/429 , H05K2201/0776
摘要： A package component includes a first substrate and a first conductive layer. The first substrate has a first surface and a second surface opposite to the first surface. The first conductive layer is disposed over the first surface of the first substrate. The first conductive layer includes a first conductive feature and a second conductive feature over the first conductive feature. The second conductive features covers a portion of the first conductive feature. A resistance of the second conductive feature is lower than a resistance of the second conductive feature. The first substrate includes a single-sided or a double-sided copper-clad laminate.
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