公开(公告)号：US20240237551A1

公开(公告)日：2024-07-11

申请号：US18615459

申请日：2024-03-25

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tai-Yen Peng ,  Hui-Hsien Wei ,  Han-Ting Lin ,  Sin-Yi Yang ,  Yu-Shu Chen ,  An-Shen Chang ,  Qiang Fu ,  Chen-Jung Wang

IPC: H10N50/80 ,  G11C11/16 ,  H10B61/00 ,  H10N50/01 ,  H10N50/85

CPC classification number: H10N50/80 ,  G11C11/161 ,  H10B61/20 ,  H10N50/01 ,  G11C11/1655 ,  G11C11/1657 ,  H10N50/85

Abstract: In an embodiment, a method includes: forming a first inter-metal dielectric (IMD) layer over a semiconductor substrate; forming a bottom electrode layer over the first IMD layer; forming a magnetic tunnel junction (MTJ) film stack over the bottom electrode layer; forming a first top electrode layer over the MTJ film stack; forming a protective mask covering a first region of the first top electrode layer, a second region of the first top electrode layer being uncovered by the protective mask; forming a second top electrode layer over the protective mask and the first top electrode layer; and patterning the second top electrode layer, the first top electrode layer, the MTJ film stack, the bottom electrode layer, and the first IMD layer with an ion beam etching (IBE) process to form a MRAM cell, where the protective mask is etched during the IBE process.

公开(公告)号：US11856869B2

公开(公告)日：2023-12-26

申请号：US17809573

申请日：2022-06-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Yu-Feng Yin ,  Tai-Yen Peng ,  An-Shen Chang ,  Han-Ting Tsai ,  Qiang Fu ,  Chung-Te Lin

IPC: H10N50/80 ,  H01L21/768 ,  H01L23/522 ,  H10N50/01

CPC classification number: H10N50/80 ,  H01L21/7684 ,  H01L23/5226 ,  H10N50/01

Abstract: The present disclosure provides a semiconductor structure, including a first metal line over a first region of the substrate, a first magnetic tunnel junction (MTJ) and a second MTJ over the first region of the substrate, and a top electrode extending over the first MTJ and the second MTJ, wherein the top electrode includes a protruding portion at a bottom surface of the top electrode.

公开(公告)号：US11417832B2

公开(公告)日：2022-08-16

申请号：US17008000

申请日：2020-08-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Yu-Feng Yin ,  Tai-Yen Peng ,  An-Shen Chang ,  Han-Ting Tsai ,  Qiang Fu ,  Chung-Te Lin

IPC: H01L43/02 ,  H01L21/768 ,  H01L23/522 ,  H01L43/12

Abstract: The present disclosure provides a semiconductor structure, including a substrate, including a first region and a second region adjacent to the first region, a magnetic tunnel junction (MTJ) over the first region, a spacer on a sidewall of the MTJ, a hard mask over the MTJ, a first dielectric layer laterally surrounding the spacer and the hard mask, a top electrode over the hard mask, and an etch stop stack laterally surrounding the top electrode.

公开(公告)号：US20210226118A1

公开(公告)日：2021-07-22

申请号：US16746158

申请日：2020-01-17

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tai-Yen Peng ,  Hui-Hsien Wei ,  Han-Ting Lin ,  Sin-Yi Yang ,  Yu-Shu Chen ,  An-Shen Chang ,  Qiang Fu ,  Chen-Jung Wang

IPC: H01L43/02 ,  H01L43/12 ,  H01L27/22 ,  G11C11/16

Abstract: In an embodiment, a method includes: forming a first inter-metal dielectric (IMD) layer over a semiconductor substrate; forming a bottom electrode layer over the first IMD layer; forming a magnetic tunnel junction (MTJ) film stack over the bottom electrode layer; forming a first top electrode layer over the MTJ film stack; forming a protective mask covering a first region of the first top electrode layer, a second region of the first top electrode layer being uncovered by the protective mask; forming a second top electrode layer over the protective mask and the first top electrode layer; and patterning the second top electrode layer, the first top electrode layer, the MTJ film stack, the bottom electrode layer, and the first IMD layer with an ion beam etching (IBE) process to form a MRAM cell, where the protective mask is etched during the IBE process.

公开(公告)号：US20220336727A1

公开(公告)日：2022-10-20

申请号：US17854289

申请日：2022-06-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tai-Yen Peng ,  Hui-Hsien Wei ,  Han-Ting Lin ,  Sin-Yi Yang ,  Yu-Shu Chen ,  An-Shen Chang ,  Qiang Fu ,  Chen-Jung Wang

IPC: H01L43/02 ,  G11C11/16 ,  H01L27/22 ,  H01L43/12

Abstract: In an embodiment, a method includes: forming a first inter-metal dielectric (IMD) layer over a semiconductor substrate; forming a bottom electrode layer over the first IMD layer; forming a magnetic tunnel junction (MTJ) film stack over the bottom electrode layer; forming a first top electrode layer over the MTJ film stack; forming a protective mask covering a first region of the first top electrode layer, a second region of the first top electrode layer being uncovered by the protective mask; forming a second top electrode layer over the protective mask and the first top electrode layer; and patterning the second top electrode layer, the first top electrode layer, the MTJ film stack, the bottom electrode layer, and the first IMD layer with an ion beam etching (IBE) process to form a MRAM cell, where the protective mask is etched during the IBE process.

公开(公告)号：US10862023B2

公开(公告)日：2020-12-08

申请号：US16242689

申请日：2019-01-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Tai-Yen Peng ,  Yu-Shu Chen ,  Chien Chung Huang ,  Sin-Yi Yang ,  Chen-Jung Wang ,  Han-Ting Lin ,  Jyu-Horng Shieh ,  Qiang Fu

IPC: H01L29/82 ,  H01L43/02 ,  H01L43/12 ,  H01L43/10

Abstract: The present disclosure provides a semiconductor structure, including a bottom electrode via, a top surface of the bottom electrode via having a first width, a barrier layer surrounding the bottom electrode via, and a magnetic tunneling junction (MTJ) over the bottom electrode via, a bottom of the MTJ having a second width, the first width being narrower than the second width.

公开(公告)号：US11387406B2

公开(公告)日：2022-07-12

申请号：US16746158

申请日：2020-01-17

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tai-Yen Peng ,  Hui-Hsien Wei ,  Han-Ting Lin ,  Sin-Yi Yang ,  Yu-Shu Chen ,  An-Shen Chang ,  Qiang Fu ,  Chen-Jung Wang

IPC: H01L43/02 ,  H01L43/12 ,  H01L27/22 ,  G11C11/16 ,  H01L43/10

Abstract: In an embodiment, a method includes: forming a first inter-metal dielectric (IMD) layer over a semiconductor substrate; forming a bottom electrode layer over the first IMD layer; forming a magnetic tunnel junction (MTJ) film stack over the bottom electrode layer; forming a first top electrode layer over the MTJ film stack; forming a protective mask covering a first region of the first top electrode layer, a second region of the first top electrode layer being uncovered by the protective mask; forming a second top electrode layer over the protective mask and the first top electrode layer; and patterning the second top electrode layer, the first top electrode layer, the MTJ film stack, the bottom electrode layer, and the first IMD layer with an ion beam etching (IBE) process to form a MRAM cell, where the protective mask is etched during the IBE process.

公开(公告)号：US11968908B2

公开(公告)日：2024-04-23

申请号：US17854289

申请日：2022-06-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tai-Yen Peng ,  Hui-Hsien Wei ,  Han-Ting Lin ,  Sin-Yi Yang ,  Yu-Shu Chen ,  An-Shen Chang ,  Qiang Fu ,  Chen-Jung Wang

IPC: H10N50/80 ,  G11C11/16 ,  H10B61/00 ,  H10N50/01 ,  H10N50/85

CPC classification number: H10N50/80 ,  G11C11/161 ,  H10B61/20 ,  H10N50/01 ,  G11C11/1655 ,  G11C11/1657 ,  H10N50/85

Abstract: In an embodiment, a method includes: forming a first inter-metal dielectric (IMD) layer over a semiconductor substrate; forming a bottom electrode layer over the first IMD layer; forming a magnetic tunnel junction (MTJ) film stack over the bottom electrode layer; forming a first top electrode layer over the MTJ film stack; forming a protective mask covering a first region of the first top electrode layer, a second region of the first top electrode layer being uncovered by the protective mask; forming a second top electrode layer over the protective mask and the first top electrode layer; and patterning the second top electrode layer, the first top electrode layer, the MTJ film stack, the bottom electrode layer, and the first IMD layer with an ion beam etching (IBE) process to form a MRAM cell, where the protective mask is etched during the IBE process.

公开(公告)号：US11944017B2

公开(公告)日：2024-03-26

申请号：US18312723

申请日：2023-05-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Tai-Yen Peng ,  Yu-Shu Chen ,  Chien Chung Huang ,  Sin-Yi Yang ,  Chen-Jung Wang ,  Han-Ting Lin ,  Jyu-Horng Shieh ,  Qiang Fu

IPC: H10N50/80 ,  H10N50/01 ,  H10N50/85

CPC classification number: H10N50/80 ,  H10N50/01 ,  H10N50/85

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes an insulation layer. A bottom electrode via is disposed in the insulation layer. The bottom electrode via includes a conductive portion and a capping layer over the conductive portion. A barrier layer surrounds the bottom electrode via. A magnetic tunneling junction (MTJ) is disposed over the bottom electrode via.

公开(公告)号：US11683991B2

公开(公告)日：2023-06-20

申请号：US17103577

申请日：2020-11-24

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Tai-Yen Peng ,  Yu-Shu Chen ,  Chien Chung Huang ,  Sin-Yi Yang ,  Chen-Jung Wang ,  Han-Ting Lin ,  Jyu-Horng Shieh ,  Qiang Fu

IPC: H10N50/80 ,  H10N50/01 ,  H10N50/85 ,  H01L43/02 ,  H01L43/12 ,  H01L43/10

CPC classification number: H01L43/02 ,  H01L43/10 ,  H01L43/12

Abstract: The present disclosure provides a method for manufacturing semiconductor structure, including forming an insulation layer, forming a first via trench in the insulation layer, forming a barrier layer in the first via trench, forming a bottom electrode via in the first via trench, forming a magnetic tunneling junction (MTJ) layer above the bottom electrode via, and performing an ion beam etching operation, including patterning the MTJ layer to form an MTJ and removing a portion of the insulation layer from a top surface.