公开(公告)号：US20180197856A1

公开(公告)日：2018-07-12

申请号：US15911263

申请日：2018-03-05

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chung-Yen Chou ,  Sheng-De Liu ,  Fu-Chih Yang ,  Shih-Chang Liu ,  Chia-Shiung Tsai

IPC分类号： H01L27/088 ,  H01L27/06 ,  H01L27/085 ,  H01L29/51 ,  H01L29/66 ,  H01L29/778 ,  H01L21/8252 ,  H01L29/20 ,  H01L29/10

CPC分类号： H01L27/088 ,  H01L21/8252 ,  H01L27/0605 ,  H01L27/085 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/517 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/66522 ,  H01L29/778 ,  H01L29/7786

摘要： A semiconductor structure with a MISFET and a HEMT region includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A third III-V compound layer is disposed on the second III-V compound layer is different from the second III-V compound layer in composition. A source feature and a drain feature are disposed in each of the MISFET and HEMT regions on the third III-V compound layer. A gate electrode is disposed over the second III-V compound layer between the source feature and the drain feature. A gate dielectric layer is disposed under the gate electrode in the MISFET region but above the top surface of the third III-V compound layer.

公开(公告)号：US09418901B2

公开(公告)日：2016-08-16

申请号：US14515392

申请日：2014-10-15

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chung-Yen Chou ,  Sheng-De Liu ,  Fu-Chih Yang ,  Shih-Chang Liu ,  Chia-Shiung Tsai

IPC分类号： H01L29/66 ,  H01L21/8252 ,  H01L29/778 ,  H01L27/06 ,  H01L27/085 ,  H01L29/51 ,  H01L29/10 ,  H01L29/20

CPC分类号： H01L27/088 ,  H01L21/8252 ,  H01L27/0605 ,  H01L27/085 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/517 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/66522 ,  H01L29/778 ,  H01L29/7786

摘要： A semiconductor structure with a MISFET and a HEMT region includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A third III-V compound layer is disposed on the second III-V compound layer is different from the second III-V compound layer in composition. A source feature and a drain feature are disposed in each of the MISFET and HEMT regions on the third III-V compound layer. A gate electrode is disposed over the second III-V compound layer between the source feature and the drain feature. A gate dielectric layer is disposed under the gate electrode in the MISFET region but above the top surface of the third III-V compound layer.

摘要翻译： 具有MISFET和HEMT区域的半导体结构包括第一III-V族化合物层。 第二III-V化合物层设置在第一III-V化合物层上，并且与组合物中的第一III-V化合物层不同。 配置在第二III-V化合物层上的第三III-V化合物层与组合物中的第二III-V化合物层不同。 源特征和漏极特征设置在第三III-V复合层上的每个MISFET和HEMT区域中。 栅电极设置在源特征和漏极特征之间的第二III-V化合物层之上。 栅极电介质层设置在MISFET区域中的栅电极下方，但位于第三III-V化合物层的顶表面之上。

公开(公告)号：US08912573B2

公开(公告)日：2014-12-16

申请号：US13777701

申请日：2013-02-26

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chung-Yen Chou ,  Sheng-De Liu ,  Fu-Chih Yang ,  Shih-Chang Liu ,  Chia-Shiung Tsai

IPC分类号： H01L29/66 ,  H01L29/778 ,  H01L21/338

CPC分类号： H01L27/088 ,  H01L21/8252 ,  H01L27/0605 ,  H01L27/085 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/517 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/66522 ,  H01L29/778 ,  H01L29/7786

摘要： A semiconductor structure with a MISFET and a HEMT region includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A third III-V compound layer is disposed on the second III-V compound layer is different from the second III-V compound layer in composition. A source feature and a drain feature are disposed in each of the MISFET and HEMT regions on the third III-V compound layer. A gate electrode is disposed over the second III-V compound layer between the source feature and the drain feature. A gate dielectric layer is disposed under the gate electrode in the MISFET region but above the top surface of the third III-V compound layer.

摘要翻译： 具有MISFET和HEMT区域的半导体结构包括第一III-V族化合物层。 第二III-V化合物层设置在第一III-V化合物层上，并且与组合物中的第一III-V化合物层不同。 配置在第二III-V化合物层上的第三III-V化合物层与组合物中的第二III-V化合物层不同。 源特征和漏极特征设置在第三III-V复合层上的每个MISFET和HEMT区域中。 栅电极设置在源特征和漏极特征之间的第二III-V化合物层之上。 栅极电介质层设置在MISFET区域中的栅电极下方，但位于第三III-V化合物层的顶表面之上。

公开(公告)号：US11233145B2

公开(公告)日：2022-01-25

申请号：US16846034

申请日：2020-04-10

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Sheng-De Liu ,  Chung-Yen Chou ,  Shih-Chang Liu

IPC分类号： H01L29/778 ,  H01L29/66 ,  H01L29/417 ,  H01L29/20

摘要： Present disclosure provides a method for manufacturing a semiconductor device, including providing a substrate, forming a first III-V compound layer over the substrate, forming a first passivation layer over the first III-V compound layer, forming a first opening from a top surface of the first passivation layer to the first III-V compound layer, each opening having a stair-shaped sidewall at the first passivation layer, depositing a metal layer over the first passivation layer and in the first opening, the metal layer having a second opening above the corresponding first opening, and removing a portion of the metal layer to form a source electrode and a drain electrode.

公开(公告)号：US10269948B2

公开(公告)日：2019-04-23

申请号：US15944345

申请日：2018-04-03

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Han-Chin Chiu ,  Sheng-De Liu ,  Yu-Syuan Lin ,  Yao-Chung Chang ,  Cheng-Yuan Tsai

IPC分类号： H01L29/205 ,  H01L29/778 ,  H01L29/66 ,  H01L29/20

摘要： A semiconductor structure includes a semiconductive substrate having a top surface, a III-V compound layer covering the top surface, and a passivation layer having a lower portion and an upper portion, both comprising at least one of oxide and nitride over the III-V compound layer. The semiconductor structure also includes an etch stop layer between the lower portion and the upper portion of the passivation layer, and a gate stack penetrating through the etch stop layer and landing on the lower portion of the passivation layer. The gate stack is surrounded by the etch stop layer.

公开(公告)号：US09748373B2

公开(公告)日：2017-08-29

申请号：US15012114

申请日：2016-02-01

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Sheng-De Liu ,  Ming-Chyi Liu ,  Chung-Yen Chou ,  Chia-Shiung Tsai

IPC分类号： H01L23/29 ,  H01L21/02 ,  H01L29/20 ,  H01L29/207 ,  H01L29/36 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H01L29/49 ,  H01L29/51 ,  H01L29/08 ,  H01L29/205 ,  H01L29/45

CPC分类号： H01L29/78 ,  H01L29/0847 ,  H01L29/205 ,  H01L29/42376 ,  H01L29/452 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66568 ,  H01L29/66583

摘要： Embodiments of the present disclosure include a MISFET device. An embodiment includes a source/drain over a substrate, a first etch stop layer on the source/drain, and a gate dielectric layer on the first etch stop layer and along the substrate. The embodiment also includes a gate electrode on the gate dielectric layer, and a second etch stop layer on the gate electrode.

公开(公告)号：US10325910B2

公开(公告)日：2019-06-18

申请号：US15911263

申请日：2018-03-05

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chung-Yen Chou ,  Sheng-De Liu ,  Fu-Chih Yang ,  Shih-Chang Liu ,  Chia-Shiung Tsai

IPC分类号： H01L27/088 ,  H01L29/66 ,  H01L29/51 ,  H01L29/778 ,  H01L29/10 ,  H01L29/20 ,  H01L21/8252 ,  H01L27/06 ,  H01L27/085

摘要： A semiconductor structure with a MISFET and a HEMT region includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A third III-V compound layer is disposed on the second III-V compound layer is different from the second III-V compound layer in composition. A source feature and a drain feature are disposed in each of the MISFET and HEMT regions on the third III-V compound layer. A gate electrode is disposed over the second III-V compound layer between the source feature and the drain feature. A gate dielectric layer is disposed under the gate electrode in the MISFET region but above the top surface of the third III-V compound layer.

公开(公告)号：US20190109223A1

公开(公告)日：2019-04-11

申请号：US16199563

申请日：2018-11-26

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Sheng-De Liu ,  Chung-Yen Chou ,  Shih-Chang Liu

IPC分类号： H01L29/778 ,  H01L29/66 ,  H01L29/417 ,  H01L29/20

摘要： Present disclosure provides a method for manufacturing a semiconductor device, including providing a substrate, forming a first III-V compound layer over the substrate, forming a first passivation layer over the first III-V compound layer, forming a first opening from a top surface of the first passivation layer to the first III-V compound layer, each opening having a stair-shaped sidewall at the first passivation layer, depositing a metal layer over the first passivation layer and in the first opening, the metal layer having a second opening above the corresponding first opening, and removing a portion of the metal layer to form a source electrode and a drain electrode.

公开(公告)号：US09911734B2

公开(公告)日：2018-03-06

申请号：US15224263

申请日：2016-07-29

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chung-Yen Chou ,  Sheng-De Liu ,  Fu-Chih Yang ,  Shih-Chang Liu ,  Chia-Shiung Tsai

IPC分类号： H01L27/088 ,  H01L29/66 ,  H01L29/51 ,  H01L29/778 ,  H01L29/10 ,  H01L29/20 ,  H01L21/8252 ,  H01L27/06 ,  H01L27/085

CPC分类号： H01L27/088 ,  H01L21/8252 ,  H01L27/0605 ,  H01L27/085 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/517 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/66522 ,  H01L29/778 ,  H01L29/7786

摘要： A semiconductor structure with a MISFET and a HEMT region includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A third III-V compound layer is disposed on the second III-V compound layer is different from the second III-V compound layer in composition. A source feature and a drain feature are disposed in each of the MISFET and HEMT regions on the third III-V compound layer. A gate electrode is disposed over the second III-V compound layer between the source feature and the drain feature. A gate dielectric layer is disposed under the gate electrode in the MISFET region but above the top surface of the third III-V compound layer.

公开(公告)号：US09941398B2

公开(公告)日：2018-04-10

申请号：US15072992

申请日：2016-03-17

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Han-Chin Chiu ,  Sheng-De Liu ,  Yu-Syuan Lin ,  Yao-Chung Chang ,  Cheng-Yuan Tsai

IPC分类号： H01L29/778 ,  H01L29/205 ,  H01L29/66

CPC分类号： H01L29/7784 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66462 ,  H01L29/7783

摘要： A semiconductor structure comprises a semiconductive substrate comprising a top surface, a III-V compound layer over the semiconductive substrate, and a first passivation layer over the III-V compound layer. The semiconductor structure also includes an etch stop layer over the first passivation layer. The semiconductor structure further includes a gate stack over the first passivation layer and surrounded by the etch stop layer.