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公开(公告)号:US20160043051A1
公开(公告)日:2016-02-11
申请号:US14455615
申请日:2014-08-08
发明人: Yen-Liang LIN , Mirng-Ji LII , Tin-Hao KUO , Chen-Shien CHEN , Yu-Feng CHEN , Sheng-Yu WU
IPC分类号: H01L23/00 , H01L25/065 , H01L21/48 , H01L23/498 , H01L23/522
CPC分类号: H01L24/17 , H01L21/486 , H01L23/49811 , H01L23/49827 , H01L23/49838 , H01L23/50 , H01L24/11 , H01L24/13 , H01L24/14 , H01L2224/13014 , H01L2224/13017 , H01L2224/13111 , H01L2224/13147 , H01L2224/16235 , H01L2224/16237 , H01L2224/16238 , H01L2224/1705 , H01L2224/81191 , H01L2224/81385 , H01L2224/81815 , H01L2924/13091 , H01L2924/15311 , H01L2924/3511 , H01L2924/3512 , H01L2924/3841 , H01L2924/00 , H01L2924/00012 , H01L2924/00014 , H01L2924/01083 , H01L2924/01029 , H01L2924/01047 , H01L2924/014
摘要: The present disclosure provides a semiconductor package, including a semiconductor die and a substrate having a first surface electrically coupled to the semiconductor die and a second surface opposing to the first surface. The first surface includes a core region having a plurality of landing pads and a periphery region surrounding the core region and having a plurality of landing traces. A pitch of the landing pads is from about 55 μm to about 280 μm. The semiconductor die includes a third surface facing the first surface of the substrate and a fourth surface opposing to the third surface. The third surface includes a plurality of elongated bump positioned correspondingly to the landing pads and the landing traces of the substrate, and the elongated bump includes a long axis and a short axis perpendicular to the long axis on a cross section thereof.
摘要翻译: 本公开提供了半导体封装,其包括半导体管芯和具有电耦合到半导体管芯的第一表面的衬底和与第一表面相对的第二表面。 第一表面包括具有多个着陆焊盘的芯区域和围绕芯区域并具有多个着陆迹线的外围区域。 着陆垫的间距为约55μm至约280μm。 半导体管芯包括面向衬底的第一表面的第三表面和与第三表面相对的第四表面。 第三表面包括对应于基板的着陆焊盘和着陆迹线定位的多个细长凸块,并且细长凸块包括在其横截面上与长轴垂直的长轴和短轴。