公开(公告)号：US20220293650A1

公开(公告)日：2022-09-15

申请号：US17830707

申请日：2022-06-02

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chia-Yu WEI ,  Fu-Cheng CHANG ,  Hsin-Chi CHEN ,  Ching-Hung KAO ,  Chia-Pin CHENG ,  Kuo-Cheng LEE ,  Hsun-Ying HUANG ,  Yen-Liang LIN

IPC分类号： H01L27/146 ,  H01L29/423 ,  H01L29/78 ,  H01L29/06

摘要： A semiconductor device includes a plurality of isolation structures, wherein each isolation structure of the plurality of isolation structures is spaced from an adjacent isolation structure of the plurality of isolation structures in a first direction. The semiconductor device further includes a gate structure. The gate structure includes a top surface; a first sidewall angled at a non-perpendicular angle with respect to the top surface; and a second sidewall angled with respect to the top surface. The gate structure further includes a first horizontal surface extending between the first sidewall and the second sidewall, wherein the first horizontal surface is parallel to the top surface, and a dimension of the gate structure in a second direction, perpendicular to the first direction, is less than a dimension of each of the plurality of isolation structures in the second direction.

公开(公告)号：US20230378205A1

公开(公告)日：2023-11-23

申请号：US18362507

申请日：2023-07-31

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chia-Yu WEI ,  Fu-Cheng CHANG ,  Hsin-Chi CHEN ,  Ching-Hung KAO ,  Chia-Pin CHENG ,  Kuo-Cheng LEE ,  Hsun-Ying HUANG ,  Yen-Liang LIN

IPC分类号： H01L27/146 ,  H01L29/423 ,  H01L29/06 ,  H01L29/78

CPC分类号： H01L27/14614 ,  H01L27/14643 ,  H01L29/42376 ,  H01L29/0653 ,  H01L29/7853 ,  H01L29/4236 ,  H01L29/78

摘要： A semiconductor device includes a plurality of isolation structures, wherein each isolation structure of the plurality of isolation structures is spaced from an adjacent isolation structure of the plurality of isolation structures. The semiconductor device further includes a gate structure. The gate structure includes a first sidewall and a second sidewall angled with respect to the first sidewall. The gate structure further includes a first surface extending between the first sidewall and the second sidewall, wherein a dimension of the gate structure in a first direction is less than a dimension of each of the plurality of isolation structures in the first direction.

公开(公告)号：US20160043051A1

公开(公告)日：2016-02-11

申请号：US14455615

申请日：2014-08-08

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Yen-Liang LIN ,  Mirng-Ji LII ,  Tin-Hao KUO ,  Chen-Shien CHEN ,  Yu-Feng CHEN ,  Sheng-Yu WU

IPC分类号： H01L23/00 ,  H01L25/065 ,  H01L21/48 ,  H01L23/498 ,  H01L23/522

CPC分类号： H01L24/17 ,  H01L21/486 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/50 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L2224/13014 ,  H01L2224/13017 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/1705 ,  H01L2224/81191 ,  H01L2224/81385 ,  H01L2224/81815 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/3841 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01083 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/014

摘要： The present disclosure provides a semiconductor package, including a semiconductor die and a substrate having a first surface electrically coupled to the semiconductor die and a second surface opposing to the first surface. The first surface includes a core region having a plurality of landing pads and a periphery region surrounding the core region and having a plurality of landing traces. A pitch of the landing pads is from about 55 μm to about 280 μm. The semiconductor die includes a third surface facing the first surface of the substrate and a fourth surface opposing to the third surface. The third surface includes a plurality of elongated bump positioned correspondingly to the landing pads and the landing traces of the substrate, and the elongated bump includes a long axis and a short axis perpendicular to the long axis on a cross section thereof.

摘要翻译： 本公开提供了半导体封装，其包括半导体管芯和具有电耦合到半导体管芯的第一表面的衬底和与第一表面相对的第二表面。 第一表面包括具有多个着陆焊盘的芯区域和围绕芯区域并具有多个着陆迹线的外围区域。 着陆垫的间距为约55μm至约280μm。 半导体管芯包括面向衬底的第一表面的第三表面和与第三表面相对的第四表面。 第三表面包括对应于基板的着陆焊盘和着陆迹线定位的多个细长凸块，并且细长凸块包括在其横截面上与长轴垂直的长轴和短轴。

公开(公告)号：US20180166481A1

公开(公告)日：2018-06-14

申请号：US15591689

申请日：2017-05-10

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chia-Yu WEI ,  Fu-Cheng CHANG ,  Hsin-Chi CHEN ,  Ching-Hung KAO ,  Chia-Pin CHENG ,  Kuo-Cheng LEE ,  Hsun-Ying HUANG ,  Yen-Liang LIN

IPC分类号： H01L27/146 ,  H01L29/06 ,  H01L27/088 ,  H01L29/40 ,  H01L29/423

摘要： A gate structure includes a gate and a first isolation structure having a top surface and a bottom surface. The gate includes a first sidewall adjacent to the first isolation structure, a second sidewall, a first horizontal surface adjacent to a bottom edge of the first sidewall and a bottom edge of the second sidewall, the first horizontal surface being between the top surface of the first isolation structure and the bottom surface of the first isolation structure. The gate also includes a second horizontal surface adjacent to a top edge of the second sidewall. An effective channel width defined by the gate structure includes a height of the second sidewall and a width of the second horizontal surface.

公开(公告)号：US20200185440A1

公开(公告)日：2020-06-11

申请号：US16790386

申请日：2020-02-13

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chia-Yu WEI ,  Fu-Cheng CHANG ,  Hsin-Chi CHEN ,  Ching-Hung KAO ,  Chia-Pin CHENG ,  Kuo-Cheng LEE ,  Hsun-Ying HUANG ,  Yen-Liang LIN

IPC分类号： H01L27/146 ,  H01L29/423 ,  H01L29/06 ,  H01L29/78

摘要： A gate structure includes a gate and a first isolation structure having a top surface and a bottom surface. The gate includes a first sidewall adjacent to the first isolation structure, a second sidewall, a first horizontal surface adjacent to a bottom edge of the first sidewall and a bottom edge of the second sidewall, the first horizontal surface being between the top surface of the first isolation structure and the bottom surface of the first isolation structure. The gate also includes a second horizontal surface adjacent to a top edge of the second sidewall. An effective channel width defined by the gate structure includes a height of the second sidewall and a width of the second horizontal surface.

公开(公告)号：US20150318253A1

公开(公告)日：2015-11-05

申请号：US14800934

申请日：2015-07-16

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chih-Horng CHANG ,  Tin-Hao KUO ,  Chen-Shien CHEN ,  Yen-Liang LIN

IPC分类号： H01L23/00

CPC分类号： H01L24/16 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/81 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05552 ,  H01L2224/05572 ,  H01L2224/05599 ,  H01L2224/10145 ,  H01L2224/11849 ,  H01L2224/13011 ,  H01L2224/13012 ,  H01L2224/13015 ,  H01L2224/13018 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/14051 ,  H01L2224/1412 ,  H01L2224/14152 ,  H01L2224/14153 ,  H01L2224/16238 ,  H01L2224/81191 ,  H01L2224/81345 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/2064 ,  Y10T428/12493 ,  Y10T428/24479 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/00

摘要： A bump structure includes a first end; and a second end opposite the first end. The bump structure further includes a side connected between the first end and the second end, wherein the side comprises a recess for a reflowed solder material to fill, and the recess defines a first surface adjacent to the first end and a second surface adjacent to the second end.

摘要翻译： 凸块结构包括第一端; 以及与第一端相对的第二端。 凸起结构还包括连接在第一端和第二端之间的侧面，其中侧面包括用于回流焊料材料填充的凹槽，凹部限定与第一端相邻的第一表面和邻近第一端的第二表面 第二端

公开(公告)号：US20150084186A1

公开(公告)日：2015-03-26

申请号：US14507189

申请日：2014-10-06

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chih-Horng CHANG ,  Tin-Hao KUO ,  Chen-Shien CHEN ,  Yen-Liang LIN

IPC分类号： H01L23/00

CPC分类号： H01L24/16 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/81 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05552 ,  H01L2224/05572 ,  H01L2224/05599 ,  H01L2224/10145 ,  H01L2224/11849 ,  H01L2224/13011 ,  H01L2224/13012 ,  H01L2224/13015 ,  H01L2224/13018 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/14051 ,  H01L2224/1412 ,  H01L2224/14152 ,  H01L2224/14153 ,  H01L2224/16238 ,  H01L2224/81191 ,  H01L2224/81345 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/2064 ,  Y10T428/12493 ,  Y10T428/24479 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/00

摘要： A bump structure includes a first end, and a second end opposite the first end. The bump structure further includes a first side connected between the first end and the second end. The bump structure further includes a second side opposite the first side. The second side is connected between the first end and the second end, and the second side comprises a recess for a reflowed solder material to fill.

摘要翻译： 凸块结构包括第一端和与第一端相对的第二端。 凸起结构还包括连接在第一端和第二端之间的第一侧。 凸起结构还包括与第一侧相对的第二侧。 第二侧连接在第一端和第二端之间，第二侧包括用于填充回流焊料的凹部。

公开(公告)号：US20240347327A1

公开(公告)日：2024-10-17

申请号：US18748650

申请日：2024-06-20

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yen-Liang LIN ,  Yu-Kang HUANG ,  Yu-Chuan TAI

IPC分类号： H01J37/34 ,  C23C14/18 ,  C23C14/35 ,  C23C14/54 ,  H01J37/32

CPC分类号： H01J37/345 ,  C23C14/185 ,  C23C14/35 ,  C23C14/54 ,  H01J37/32449 ,  H01J37/3426 ,  H01J37/3464 ,  H01J37/3476 ,  H01J37/32082 ,  H01J2237/24564 ,  H01J2237/332

摘要： Some implementations described herein provide a physical vapor deposition tool. The physical vapor deposition tool includes a magnet component, a single cathode, and a power circuit for biasing a pedestal that supports a semiconductor substrate. During a deposition operation that deposits an inert metal material, the physical vapor deposition tool may modulate an electromagnetic field emanating from the magnet component that includes spiral-shaped bands having different ranges of magnetic strength. The physical vapor deposition tool may have an increased throughput relative to a physical vapor deposition tool without the magnet component, the single cathode, and the power circuit. Additionally, or alternatively, the inert metal material may have a grain size that is greater relative to a grain size of an inert metal material deposited using the physical vapor deposition tool without the magnet component, the single cathode, and the power circuit.

公开(公告)号：US20240096609A1

公开(公告)日：2024-03-21

申请号：US18162274

申请日：2023-01-31

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yen-Liang LIN ,  Yu-Kang HUANG ,  Yu-Chuan TAI

IPC分类号： H01J37/34 ,  C23C14/18 ,  C23C14/35 ,  C23C14/54 ,  H01J37/32

CPC分类号： H01J37/345 ,  C23C14/185 ,  C23C14/35 ,  C23C14/54 ,  H01J37/32449 ,  H01J37/3426 ,  H01J37/3464 ,  H01J37/3476 ,  H01J37/32082 ,  H01J2237/24564 ,  H01J2237/332

摘要： The physical vapor deposition tool includes a magnet component, a single cathode, and a power circuit for biasing a pedestal that supports a semiconductor substrate. During a deposition operation that deposits an inert metal material, the physical vapor deposition tool may modulate an electromagnetic field emanating from the magnet component that includes spiral-shaped bands having different ranges of magnetic strength. The physical vapor deposition tool may have an increased throughput relative to a physical vapor deposition tool without the magnet component, the single cathode, and the power circuit. Additionally, or alternatively, the inert metal material may have a grain size that is greater relative to a grain size of an inert metal material deposited using the physical vapor deposition tool without the magnet component, the single cathode, and the power circuit.

公开(公告)号：US20220367391A1

公开(公告)日：2022-11-17

申请号：US17873835

申请日：2022-07-26

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chia-Yu WEI ,  Cheng-Yuan LI ,  Yen-Liang LIN ,  Kuo-Cheng LEE ,  Hsun-Ying HUANG ,  Hsin-Chi CHEN

IPC分类号： H01L23/00 ,  H01L27/146

摘要： A semiconductor structure is provided. The semiconductor structure includes a first semiconductor device. The semiconductor structure includes a first semiconductor device and a second semiconductor device. The first semiconductor device includes a first oxide layer formed below the a first substrate, a first bonding layer formed below the first oxide layer, and a first bonding via formed through the first bonding layer and the first oxide layer. The second semiconductor device includes a second oxide layer formed over a second substrate, a second bonding layer formed over the second oxide layer, and a second bonding via formed through the second bonding layer and the second oxide layer. The semiconductor structure also includes a bonding structure between the first substrate and the second substrate, and the bonding structure includes the first bonding via bonded to the second bonding via.