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    SEMICONDUCTOR DEVICE WITH REDUCED TRAP DEFECT AND METHOD OF FORMING THE SAME
    2.
    发明申请
    SEMICONDUCTOR DEVICE WITH REDUCED TRAP DEFECT AND METHOD OF FORMING THE SAME 有权

    公开(公告)号：US20210020761A1

    公开(公告)日：2021-01-21

    申请号：US16514373

    申请日：2019-07-17

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

    发明人： CHUN HSIUNG TSAI ,  KUO-FENG YU ,  YU-MING LIN ,  CLEMENT HSINGJEN WANN

    IPC分类号： H01L29/66 ,  H01L21/02 ,  H01L29/08 ,  H01L21/265

    摘要： A method of manufacturing a semiconductor device includes: providing a substrate comprising a surface; depositing a first dielectric layer and a second dielectric layer over the substrate; forming a dummy gate electrode over the second dielectric layer; forming a gate spacer surrounding the dummy gate electrode; forming lightly-doped source/drain (LDD) regions in the substrate on two sides of the gate spacer; forming source/drain regions in the respective LDD regions; removing the dummy gate electrode to form a replacement gate; forming an inter-layer dielectric (ILD) layer over the replacement gate and the source/drain regions; and performing a treatment by introducing a trap-repairing element into at least one of the gate spacer, the second dielectric layer, the surface and the LDD regions at a time before the forming of the source/drain regions or subsequent to the formation of the ILD layer.

    METHOD FOR FORMING SEMICONDUCTOR STRUCTURE
    3.
    发明申请
    METHOD FOR FORMING SEMICONDUCTOR STRUCTURE 有权

    公开(公告)号：US20220367665A1

    公开(公告)日：2022-11-17

    申请号：US17815253

    申请日：2022-07-27

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

    发明人： YEN-CHIEH HUANG ,  HAI-CHING CHEN ,  YU-MING LIN ,  CHUNG-TE LIN

    IPC分类号： H01L29/51 ,  H01L21/28 ,  H01L29/78

    摘要： A method for forming a semiconductor structure is provided. The method includes following operations. A layer stack is formed over the substrate. The formation of the layer stack includes the following sub-operations: a blocking layer is formed over the substrate, a lower conductive layer is formed over the blocking layer, a first seed layer is formed over the lower conductive layer, a ferroelectric layer is formed over the first seed layer, and an upper conductive layer is formed over the ferroelectric layer. The layer stack is patterned to form a gate stack over the substrate. A spacer layer is formed over sidewalls of the gate stack. A pattered interlayer dielectric layer is formed over the substrate and the gate stack. A source region and a drain region are formed in the substrate through the patterned interlayer dielectric layer.

    MEMORY DEVICE AND METHOD OF FABRICATING THE MEMORY DEVICE
    6.
    发明申请
    MEMORY DEVICE AND METHOD OF FABRICATING THE MEMORY DEVICE 有权

    公开(公告)号：US20210217847A1

    公开(公告)日：2021-07-15

    申请号：US16739868

    申请日：2020-01-10

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

    发明人： CHIH-YU CHANG ,  SAI-HOOI YEONG ,  YU-MING LIN ,  CHIH-HAO WANG

    IPC分类号： H01L29/06 ,  H01L27/11587 ,  H01L27/088 ,  G11C11/22 ,  H01L29/78 ,  H01L29/66

    摘要： The present disclosure provides a semiconductor structure, including a substrate having a memory region and a logic region, the memory region including a first group of nanosheets vertically arranged over a first region of the substrate, wherein the first group of nanosheets includes: a first semiconductor nanosheet, a second group of nanosheets vertically arranged over a second region of the substrate adjacent to the first region, wherein the second group of nanosheets includes: a second semiconductor nanosheet, and a third semiconductor nanosheet over the second semiconductor nanosheet, a first metal gate layer surrounding the first semiconductor nanosheet, and a second metal gate layer surrounding the second semiconductor nanosheet, wherein the first metal gate layer is in direct contact with the second metal gate layer.

    SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
    10.
    发明申请
    SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME 有权

    公开(公告)号：US20210217757A1

    公开(公告)日：2021-07-15

    申请号：US16738565

    申请日：2020-01-09

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

    发明人： CHIH-YU CHANG ,  SAI-HOOI YEONG ,  YU-MING LIN ,  CHIH-HAO WANG

    IPC分类号： H01L27/11507 ,  H01L49/02

    摘要： A semiconductor structure is provided. The semiconductor structure includes a substrate, a source/drain structure, a metal gate structure, a ferroelectric layer, a spacer and a metal layer. The source/drain structure is disposed over the substrate. The metal gate structure is disposed over the substrate and between the source/drain structure. The ferroelectric layer is disposed over the metal gate structure and the source/drain structure. The spacer is disposed over the ferroelectric layer. The metal layer is disposed over the ferroelectric layer and surrounded by the spacer. A method for manufacturing a semiconductor structure is also provided.