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14 条记录 (耗时 0.021 秒)

    SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE SAME
    1.
    发明申请
    SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE SAME 有权

    公开(公告)号：US20230066393A1

    公开(公告)日：2023-03-02

    申请号：US17460100

    申请日：2021-08-27

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

    发明人： YU-WEI JIANG ,  SHENG-CHIH LAI ,  KUO-CHANG CHIANG ,  HUNG-CHANG SUN ,  TSUCHING YANG ,  FENG-CHENG YANG ,  CHUNG-TE LIN

    IPC分类号： H01L27/11582

    摘要： A method includes forming a plurality of memory cells, which includes a plurality of first conductive lines over a substrate, charge-trapping layers coupled to the conductive lines, channel layers arranged adjacent to the charge-trapping layers, and a plurality of first filling regions arranged between the channel layers; etching the first filling regions to form first trenches; depositing a liner over upper surfaces of the charge-trapping layers and the channel layers and sidewalls of the first trenches; forming second filling regions in the first trenches; patterning the second filling regions to form second trenches; depositing a partition region in each of the second trenches; and removing the liner to expose the charge-trapping layers and the channel layers.

    SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE SAME
    3.
    发明申请
    SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE SAME 有权

    公开(公告)号：US20210375985A1

    公开(公告)日：2021-12-02

    申请号：US16886648

    申请日：2020-05-28

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

    发明人： GAO-MING WU ,  HAN-TING TSAI ,  CHUNG-TE LIN

    IPC分类号： H01L27/22 ,  H01L43/02 ,  G11C5/02 ,  G11C5/06 ,  H01L23/522

    摘要： A semiconductor structure, comprising a substrate and an interconnect layer disposed over a substrate and extending across a memory region and a logic region. The interconnect layer comprises a plurality of tower structures disposed in the interconnect layer within the memory region. Each tower structure comprises at least one metal interconnect structure and a magnetic tunnel junction (MTJ) structure stacked on the metal interconnect structure. The plurality of tower structures are arranged on the substrate in a XY staggered pattern. The at least one metal interconnect structure and the magnetic tunnel junction (MTJ) structure in each tower structure are substantially symmetric along a stacking direction.

    METHOD FOR FORMING SEMICONDUCTOR STRUCTURE
    5.
    发明申请
    METHOD FOR FORMING SEMICONDUCTOR STRUCTURE 有权

    公开(公告)号：US20220367665A1

    公开(公告)日：2022-11-17

    申请号：US17815253

    申请日：2022-07-27

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

    发明人： YEN-CHIEH HUANG ,  HAI-CHING CHEN ,  YU-MING LIN ,  CHUNG-TE LIN

    IPC分类号： H01L29/51 ,  H01L21/28 ,  H01L29/78

    摘要： A method for forming a semiconductor structure is provided. The method includes following operations. A layer stack is formed over the substrate. The formation of the layer stack includes the following sub-operations: a blocking layer is formed over the substrate, a lower conductive layer is formed over the blocking layer, a first seed layer is formed over the lower conductive layer, a ferroelectric layer is formed over the first seed layer, and an upper conductive layer is formed over the ferroelectric layer. The layer stack is patterned to form a gate stack over the substrate. A spacer layer is formed over sidewalls of the gate stack. A pattered interlayer dielectric layer is formed over the substrate and the gate stack. A source region and a drain region are formed in the substrate through the patterned interlayer dielectric layer.

    INTEGRATED CIRCUIT AND METHOD FOR MANUFACTURING THE SAME
    8.
    发明申请
    INTEGRATED CIRCUIT AND METHOD FOR MANUFACTURING THE SAME 有权

    公开(公告)号：US20220020916A1

    公开(公告)日：2022-01-20

    申请号：US16932639

    申请日：2020-07-17

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

    发明人： CHANG-LIN YANG ,  CHUNG-TE LIN ,  HAN-TING TSAI ,  CHIEN-HUA HUANG

    IPC分类号： H01L43/02 ,  H01L27/22 ,  H01L43/12

    摘要： An integrated circuit includes a substrate, a dielectric layer over the substrate, a plurality of cells, a plurality of spacers and a plurality of conductive particles. Each of the cells includes a bottom portion in the dielectric layer and an upper portion protruding from the dielectric layer. The spacers are disposed over the dielectric layer and partially cover the upper portions of the cells, respectively. The spacers are disconnected from each other, and cover a first area of the dielectric layer and expose a second area of the dielectric layer. The conductive particles are disposed between the first area of the dielectric layer and the spacers.