公开(公告)号：US20210242239A1

公开(公告)日：2021-08-05

申请号：US16892038

申请日：2020-06-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： YU-MING LIN ,  CHUN-CHIEH LU ,  BO-FENG YOUNG ,  HAN-JONG CHIA ,  CHENCHEN JACOB WANG ,  SAI-HOOI YEONG

IPC: H01L27/11597 ,  G11C7/18 ,  G11C8/14 ,  H01L27/11587 ,  H01L27/1159

Abstract: A semiconductor memory structure includes a semiconductor layer, a conductive layer disposed over the semiconductor layer, a gate penetrating through the conductive layer and the semiconductor layer, and an interposing layer disposed between the gate and the conductive layer and between the gate and the semiconductor layer, wherein a pair of channel regions is formed in the semiconductor layer at two sides of the gate.

公开(公告)号：US20220115586A1

公开(公告)日：2022-04-14

申请号：US17070426

申请日：2020-10-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： YA-LING LEE ,  TSANN LIN ,  HAN-JONG CHIA

IPC: H01L43/08 ,  H01L43/12 ,  H01L43/10 ,  H01L43/02 ,  G11C11/16 ,  H01L27/22 ,  G01R33/09

Abstract: A magnetic tunnel junction (MTJ) element is provided. The MTJ element includes a reference layer, a tunnel barrier layer disposed over the reference layer, a free layer disposed over the tunnel barrier layer, and a diffusion barrier layer disposed over the free layer. The MU element in accordance with the present disclosure exhibits a low resistance desired for a low-power write operation, and a high TIM coefficient desired for a low bit-error-rate (BER) read operation.

公开(公告)号：US20210210496A1

公开(公告)日：2021-07-08

申请号：US16737600

申请日：2020-01-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： HAN-JONG CHIA ,  YU-MING LIN ,  ZHIQIANG WU ,  SAI-HOOI YEONG

IPC: H01L27/1159 ,  H01L29/423 ,  H01L27/11507 ,  H01L49/02 ,  H01L21/28 ,  H01L29/78 ,  H01L29/66

Abstract: A semiconductor structure and manufacturing method thereof are provided. The semiconductor structure includes a substrate having a first surface, a plurality of ferroelectric layers stacking over the first surface, and a plurality of metal layers stacking over the first surface of the substrate, wherein each of the metal layers is on each of the ferroelectric layers. The operations of the method for manufacturing the semiconductor structure includes providing a substrate having a first surface, and forming a plurality of stack units over the first surface of the substrate The forming of each of the stack units includes the operations of forming a ferroelectric layer and forming a metal layer on the ferroelectric layer.

公开(公告)号：US20240365676A1

公开(公告)日：2024-10-31

申请号：US18770678

申请日：2024-07-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： YA-LING LEE ,  TSANN LIN ,  HAN-JONG CHIA

IPC: H10N50/10 ,  G01R33/09 ,  G11C11/16 ,  H10B61/00 ,  H10N50/01 ,  H10N50/80 ,  H10N50/85

CPC classification number: H10N50/10 ,  G01R33/093 ,  G01R33/098 ,  G11C11/161 ,  H10B61/00 ,  H10N50/01 ,  H10N50/80 ,  H10N50/85

Abstract: A magnetic tunnel junction (MTJ) element is provided. The MTJ element includes a hard bias layer, a reference layer disposed over the hard bias layer, a tunnel barrier layer disposed over the reference layer, a free layer disposed over the tunnel barrier layer, and a diffusion barrier layer disposed over the free layer wherein the diffusion barrier layer comprises an amorphous and nonmagnetic film of a form X-Z, where X is Fe or Co and Z is Hf, Y, or Zr. The MTJ element in accordance with the present disclosure exhibits a low resistance desired for a low-power write operation, and a high TMR coefficient desired for a low bit-error-rate (BER) read operation.

公开(公告)号：US20220406815A1

公开(公告)日：2022-12-22

申请号：US17351121

申请日：2021-06-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： YU-CHIEN CHIU ,  MENG-HAN LIN ,  CHUN-FU CHENG ,  HAN-JONG CHIA ,  CHUNG-WEI WU ,  ZHIQIANG WU

IPC: H01L27/11597 ,  H01L27/11587 ,  H01L29/06

Abstract: A semiconductor memory device includes a stack of alternating insulating layers and first conductive layers disposed over a substrate; a plurality of memory cell strings penetrating the stack over the substrate, each memory cell string comprising a central portion extending through the stack, a semiconductor layer surrounding the central portion, and a ferroelectric layer surrounding the semiconductor layer, and the central portion comprising a channel isolation structure and a second conductive layer and a third conductive layer at two sides of the channel isolation structure; and a plurality of cell isolation structures penetrating the conductive layers and the insulating layers over the substrate and disposed between two memory cell strings, each cell isolation structure comprising a top portion and a bottom portion adjoined to the top portion and different from the top portion.

公开(公告)号：US20220302171A1

公开(公告)日：2022-09-22

申请号：US17837982

申请日：2022-06-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： BO-FENG YOUNG ,  HAN-JONG CHIA ,  SAI-HOOI YEONG ,  YU-MING LIN ,  CHUNG-TE LIN

IPC: H01L27/11597 ,  H01L27/06 ,  H01L23/48 ,  H01L27/11 ,  H01L27/1159 ,  H01L21/822 ,  H01L29/78 ,  H01L29/66 ,  H01L21/768 ,  H01L27/11592

Abstract: The present disclosure provides a semiconductor structure, including a first layer including a logic device, a second layer over the first layer including a first type memory device, and a though silicon via (TSV) electrically connecting the logic device and the first type memory device.

公开(公告)号：US20210242240A1

公开(公告)日：2021-08-05

申请号：US16904557

申请日：2020-06-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： BO-FENG YOUNG ,  HAN-JONG CHIA ,  SAI-HOOI YEONG ,  YU-MING LIN ,  CHUNG-TE LIN

IPC: H01L27/11597 ,  H01L27/06 ,  H01L23/48 ,  H01L27/11 ,  H01L27/1159 ,  H01L27/11592 ,  H01L29/78 ,  H01L29/66 ,  H01L21/768 ,  H01L21/822

Abstract: The present disclosure provides a semiconductor structure, including: a first layer including a logic device; and a second layer over the first layer, including a first type memory device, a though silicon via (TSV) electrically connecting the logic device and the first type memory device. A method of forming semiconductor structure is also disclosed.

公开(公告)号：US20240357829A1

公开(公告)日：2024-10-24

申请号：US18760062

申请日：2024-07-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： BO-FENG YOUNG ,  HAN-JONG CHIA ,  SAI-HOOI YEONG ,  YU-MING LIN ,  CHUNG-TE LIN

IPC: H10B51/20 ,  H01L21/768 ,  H01L21/822 ,  H01L23/48 ,  H01L27/06 ,  H01L29/66 ,  H01L29/78 ,  H10B10/00 ,  H10B51/30 ,  H10B51/40

CPC classification number: H10B51/20 ,  H01L21/76898 ,  H01L21/8221 ,  H01L23/481 ,  H01L27/0688 ,  H01L29/66795 ,  H01L29/6684 ,  H01L29/78391 ,  H01L29/785 ,  H10B10/12 ,  H10B51/30 ,  H10B51/40

Abstract: A semiconductor structure is provided. The semiconductor structure includes a first layer having a logic device; a lower second layer over the first layer; an upper second layer over the lower second layer; a first isolation layer sandwiching by the first layer and the lower second layer; and a plurality of though layer via structures (TLV) penetrating the lower second layer, the upper second layer, the first isolation layer, and the second isolation layer. The lower second layer has a lower memory device. The upper second layer has an upper memory device. A channel length of the upper memory device is longer than a channel length of the lower memory device.

公开(公告)号：US20230337547A1

公开(公告)日：2023-10-19

申请号：US18331154

申请日：2023-06-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： YA-LING LEE ,  TSANN LIN ,  HAN-JONG CHIA

IPC: H01L29/82 ,  G01R33/09 ,  G11C11/16

CPC classification number: H10N50/10 ,  H10N50/80 ,  H10N50/85 ,  G01R33/098 ,  G11C11/161 ,  H10N50/01 ,  G01R33/093 ,  H10B61/00

Abstract: A magnetic tunnel junction (MTJ) element is provided. The MTJ element includes a reference layer, a tunnel barrier layer disposed over the reference layer, a free layer disposed over the tunnel barrier layer, and a diffusion barrier layer disposed over the free layer. The MTJ element in accordance with the present disclosure exhibits a low resistance desired for a low-power write operation, and a high TMR coefficient desired for a low bit-error-rate (BER) read operation.

公开(公告)号：US20230320102A1

公开(公告)日：2023-10-05

申请号：US18331138

申请日：2023-06-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： YU-CHIEN CHIU ,  MENG-HAN LIN ,  CHUN-FU CHENG ,  HAN-JONG CHIA ,  CHUNG-WEI WU ,  ZHIQIANG WU

IPC: H10B51/20 ,  H01L29/06 ,  H10B51/10 ,  H10B51/30

CPC classification number: H10B51/20 ,  H01L29/0649 ,  H10B51/10 ,  H10B51/30

Abstract: A semiconductor memory device includes a stack of alternating insulating layers and first conductive layers disposed over a substrate; a plurality of memory cell strings penetrating the stack over the substrate, each memory cell string comprising a central portion extending through the stack, a semiconductor layer surrounding the central portion, and a ferroelectric layer surrounding the semiconductor layer, and the central portion comprising a channel isolation structure and a second conductive layer and a third conductive layer at two sides of the channel isolation structure; and a plurality of cell isolation structures penetrating the conductive layers and the insulating layers over the substrate and disposed between two memory cell strings, each cell isolation structure comprising a top portion and a bottom portion adjoined to the top portion and different from the top portion.