公开(公告)号：US20240077925A1

公开(公告)日：2024-03-07

申请号：US18505037

申请日：2023-11-08

Applicant: Texas Instruments Incorporated

Inventor： Jose Luis FLORES ,  Gary Augustine COOPER ,  Amritpal Singh MUNDRA ,  Anthony LELL ,  Jason Lynn PECK

IPC: G06F1/3203 ,  G06F11/36

CPC classification number: G06F1/3203 ,  G06F11/3656

Abstract: Circuits, systems and methods are provided. A circuit includes a subsystem, an interface, and a debugger. The interface includes power processing and management (PPM) circuitry coupled to the subsystem, and arbitration logic coupled to the PPM circuitry. In operation, the debugger issues a debug request to the arbitration logic to perform a debug operation on the subsystem, and, in response to the debug request, the arbitration logic provides an interrupt associated with the subsystem to the PPM circuitry. The PPM circuitry, in response to the interrupt and a determination that the subsystem is OFF, powers on the subsystem and provides a notification to the arbitration logic indicating that the subsystem is ON. The PPM circuitry also receives a notification from the arbitration logic that the debug operation related to the debug request is complete, and powers off the subsystem in response to that notification.

公开(公告)号：US20240296220A1

公开(公告)日：2024-09-05

申请号：US18662227

申请日：2024-05-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Kedar Satish CHITNIS ,  Mihir Narendra MODY ,  Amritpal Singh MUNDRA ,  Yashwant DUTT ,  Gregory Raymond SHURTZ ,  Robert John TIVY

IPC: G06F21/54 ,  G06F9/48 ,  G06F21/55 ,  G06F21/79

CPC classification number: G06F21/54 ,  G06F9/485 ,  G06F21/554 ,  G06F21/79

Abstract: Devices, systems and techniques for implementing freedom from interference (FFI) access rules. In an example, a device includes a set of primary components, a set of secondary components, and an interconnected coupled between the two sets of components. Each primary component of the set of primary components has an access identifier, among multiple access attributes, and an access attribute, among multiple access modes. Each secondary component of the set of secondary components is protected by a firewall. Each firewall is configured to specify, for each specific combination of an access identifier and access attribute, whether access to the associated secondary component is permitted and what type of access is permitted.

公开(公告)号：US20230185904A1

公开(公告)日：2023-06-15

申请号：US17550948

申请日：2021-12-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Kedar Satish CHITNIS ,  Mihir Narendra MODY ,  Amritpal Singh MUNDRA ,  Yashwant DUTT ,  Gregory Raymond SHURTZ ,  Robert John TIVY

IPC: G06F21/54 ,  G06F21/55 ,  G06F21/79 ,  G06F9/48

CPC classification number: G06F21/54 ,  G06F9/485 ,  G06F21/79 ,  G06F21/554

Abstract: A method of enabling memory access freedom from interference (FFI) rules, comprising: determining a first safety privilege access ID (PrivID) for a first component of a system (e.g., based on Automotive Safety Integrity Level (ASIL) attributes of tasks executed by the first component); determining a first access attribute for a first software task executing on the first component; receiving, at a first firewall component of the system, a request from the first software task to access a first memory region of a second component of the system, wherein the request specifies the first PrivID and the first access attribute; and determining, by the first firewall component, whether to permit the first software task to access the first memory region based on the first PrivID, the first access attribute, and the first memory region.

公开(公告)号：US20210208657A1

公开(公告)日：2021-07-08

申请号：US17139249

申请日：2020-12-31

Applicant: Texas Instruments Incorporated

Inventor： Jose Luis FLORES ,  Gary Augustine COOPER ,  Amritpal Singh MUNDRA ,  Anthony LELL ,  Jason Lynn PECK

IPC: G06F1/3203 ,  G06F11/36

Abstract: An integrated circuit includes: a debugger; and an interface coupled to the debugger. The interface has: arbitration logic coupled to the debugger; a power processor coupled to the arbitration logic; and a power management network coupled to the power processor. The integrated circuit also includes subsystems coupled to the interface. The debugger is configured to perform debugging operations of the subsystems via the interface.

公开(公告)号：US20200210256A1

公开(公告)日：2020-07-02

申请号：US16377404

申请日：2019-04-08

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Kedar Satish CHITNIS ,  Charles Lance FUOCO ,  Sriramakrishnan GOVINDARAJAN ,  Mihir Narendra MODY ,  William A. MILLS ,  Gregory Raymond SHURTZ ,  Amritpal Singh MUNDRA

IPC: G06F9/54 ,  G06F9/50 ,  G06F9/38 ,  G06F9/48 ,  G06F9/455

Abstract: This disclosure relates to various implementations an embedded computing system. The embedded computing system comprises a hardware accelerator (HWA) thread user and a second HWA thread user that creates and sends out message requests. The HWA thread user and the second HWA thread user is communication with a microcontroller (MCU) subsystem. The embedded computing system also comprises a first inter-processor communication (IPC) interface between the HWA thread user and the MCU subsystem and a second IPC interface between the second HWA thread user and the MCU subsystem, where the first IPC interface is isolated from the second IPC interface. The MCU subsystem is also in communication with a first domain specific HWA and a second domain specific HWA.