公开(公告)号：US20190162590A1

公开(公告)日：2019-05-30

申请号：US16191430

申请日：2018-11-14

Applicant: Texas Instruments Incorporated

Inventor： Michael Zwerg ,  Sudhanshu Khanna ,  Steven C. Bartling ,  Brian Elies ,  Krishnasawamy Nagaraj ,  Wei-Yan Shih

IPC: G01H11/08

Abstract: In described examples, each node between adjacent capacitive elements of a stack of series-coupled capacitive elements is biased during a reset mode, where each of the capacitive elements includes piezoelectric material. A strain-induced voltage is generated across each of the capacitive elements. Each of the strain-induced voltages is combined to generate a piezoelectric-responsive output signal during a sensing mode at a time different from the time of the reset mode.

公开(公告)号：US20230087653A1

公开(公告)日：2023-03-23

申请号：US17828839

申请日：2022-05-31

Applicant: Texas Instruments Incorporated

Inventor： Brian Elies

IPC: H03M1/06

Abstract: An example apparatus includes: resistor ladder circuitry including a plurality of intermediate voltage nodes; a first plurality of switches having inputs coupled to a plurality of intermediate voltage nodes and having outputs; first level decoder circuitry configured to: receive a set of input bits; and open or close ones of the first plurality of switches based on a first subset of the input bits; a second plurality of switches having inputs coupled to the outputs of the first plurality of switches and having outputs coupled to a common node; and second level decoder circuitry configured to: receive the set of input bits; and open or close ones of the second plurality of switches based on a second subset of the input bits, the first and the second subsets sharing one of the input bits, wherein the output voltage is to be coupled to the common node.

公开(公告)号：US20240340017A1

公开(公告)日：2024-10-10

申请号：US18748371

申请日：2024-06-20

Applicant: Texas Instruments Incorporated

Inventor： Brian Elies

IPC: H03M1/06 ,  H03M1/66 ,  H03M1/80 ,  H03M3/00

CPC classification number: H03M1/0612 ,  H03M1/06 ,  H03M1/66 ,  H03M1/80 ,  H03M3/00

Abstract: An example apparatus includes: resistor ladder circuitry including a plurality of intermediate voltage nodes; a first plurality of switches having inputs coupled to a plurality of intermediate voltage nodes and having outputs; first level decoder circuitry configured to: receive a set of input bits; and open or close ones of the first plurality of switches based on a first subset of the input bits; a second plurality of switches having inputs coupled to the outputs of the first plurality of switches and having outputs coupled to a common node; and second level decoder circuitry configured to: receive the set of input bits; and open or close ones of the second plurality of switches based on a second subset of the input bits, the first and the second subsets sharing one of the input bits, wherein the output voltage is to be coupled to the common node.

公开(公告)号：US12057853B2

公开(公告)日：2024-08-06

申请号：US17828839

申请日：2022-05-31

Applicant: Texas Instruments Incorporated

Inventor： Brian Elies

IPC: H03M1/66 ,  H03M1/06 ,  H03M1/80 ,  H03M3/00

CPC classification number: H03M1/0612 ,  H03M1/06 ,  H03M1/66 ,  H03M1/80 ,  H03M3/00

Abstract: An example apparatus includes: resistor ladder circuitry including a plurality of intermediate voltage nodes; a first plurality of switches having inputs coupled to a plurality of intermediate voltage nodes and having outputs; first level decoder circuitry configured to: receive a set of input bits; and open or close ones of the first plurality of switches based on a first subset of the input bits; a second plurality of switches having inputs coupled to the outputs of the first plurality of switches and having outputs coupled to a common node; and second level decoder circuitry configured to: receive the set of input bits; and open or close ones of the second plurality of switches based on a second subset of the input bits, the first and the second subsets sharing one of the input bits, wherein the output voltage is to be coupled to the common node.

公开(公告)号：US12072229B2

公开(公告)日：2024-08-27

申请号：US17462090

申请日：2021-08-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Michael Zwerg ,  Sudhanshu Khanna ,  Steven C. Bartling ,  Brian Elies ,  Krishnasawamy Nagaraj ,  Wei-Yan Shih

IPC: G01H11/08

CPC classification number: G01H11/08

Abstract: In described examples, each node between adjacent capacitive elements of a stack of series-coupled capacitive elements is biased during a reset mode, where each of the capacitive elements includes piezoelectric material. A strain-induced voltage is generated across each of the capacitive elements. Each of the strain-induced voltages is combined to generate a piezoelectric-responsive output signal during a sensing mode at a time different from the time of the reset mode.

公开(公告)号：US20210389174A1

公开(公告)日：2021-12-16

申请号：US17462090

申请日：2021-08-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Michael Zwerg ,  Sudhanshu Khanna ,  Steven C. Bartling ,  Brian Elies ,  Krishnasawamy Nagaraj ,  Wei-Yan Shih

IPC: G01H11/08

Abstract: In described examples, each node between adjacent capacitive elements of a stack of series-coupled capacitive elements is biased during a reset mode, where each of the capacitive elements includes piezoelectric material. A strain-induced voltage is generated across each of the capacitive elements. Each of the strain-induced voltages is combined to generate a piezoelectric-responsive output signal during a sensing mode at a time different from the time of the reset mode.

公开(公告)号：US11105676B2

公开(公告)日：2021-08-31

申请号：US16191430

申请日：2018-11-14

Applicant: Texas Instruments Incorporated

Inventor： Michael Zwerg ,  Sudhanshu Khanna ,  Steven C. Bartling ,  Brian Elies ,  Krishnasawamy Nagaraj ,  Wei-Yan Shih

IPC: G01H11/08

Abstract: In described examples, each node between adjacent capacitive elements of a stack of series-coupled capacitive elements is biased during a reset mode, where each of the capacitive elements includes piezoelectric material. A strain-induced voltage is generated across each of the capacitive elements. Each of the strain-induced voltages is combined to generate a piezoelectric-responsive output signal during a sensing mode at a time different from the time of the reset mode.

公开(公告)号：US20200168786A1

公开(公告)日：2020-05-28

申请号：US16201808

申请日：2018-11-27

Applicant: Texas Instruments Incorporated

Inventor： Sudhanshu Khanna ,  Michael Zwerg ,  Steven C. Bartling ,  Brian Elies ,  Krishnasawamy Nagaraj ,  Wei-Yan Shih

IPC: H01L41/08 ,  H01L41/107 ,  H01L41/04 ,  H01L41/047

Abstract: An improved differential sensor and corresponding apparatus implementing same. The differential sensor includes a substrate, an amplifier coupled to the substrate, and a plurality of highly-matched piezoelectric capacitors formed onto the substrate. A first set of the highly-matched piezoelectric capacitors are electrically coupled to a non-inverting input of the amplifier, and a second set of the highly-matched piezoelectric capacitors are electrically coupled to an inverting input of the amplifier to form an open loop differential amplifier.