公开(公告)号：US20200212896A1

公开(公告)日：2020-07-02

申请号：US16236330

申请日：2018-12-28

Applicant: Texas Instruments Incorporated

Inventor： Soman Purushothaman ,  Sankar Prasad Debnath ,  Per Torstein Roine ,  Steven C. Bartling ,  Keshav Bhaktavatson Chintamani

IPC: H03K3/037 ,  H03K3/012

Abstract: In described examples, a latch includes circuitry for latching input information. The circuitry can be precharged in response to an indication of a first mode and can latch the input information to an indication of a second mode. The latch can optionally further latch the input information in response to a node for storing the latched input information.

公开(公告)号：US09520863B2

公开(公告)日：2016-12-13

申请号：US14447911

申请日：2014-07-31

Applicant: Texas Instruments Incorporated

Inventor： Steven C. Bartling ,  Sudhanshu Khanna

IPC: H03K3/356

CPC classification number: H03K3/356008

Abstract: In an embodiment of the invention, a dual-port negative level sensitive preset data retention latch contains a clocked inverter and a dual-port latch. Data is clocked through the clocked inverter when clock signal CKT goes low, CLKZ goes high, preset control signal PRE is low and retention control signal RET is low. The dual-port latch is configured to receive the output of the clocked inverter, a second data bit D2, the clock signals CKT and CLKZ, the retain control signals RET and RETN, the preset control signal PRE and the control signals SS and SSN. The signals CKT, CLKZ, RET, RETN, PRE, SS and SSN determine whether the output of the clocked inverter or the second data bit D2 is latched in the dual-port latch. Control signals RET and RETN determine when data is stored in the dual-port latch during retention mode.

Abstract translation: 在本发明的一个实施例中，双端口负电平敏感预设数据保持锁存器包括时钟反相器和双端口锁存器。 当时钟信号CKT变低，CLKZ变为高电平，预置控制信号PRE为低电平，保持控制信号RET为低电平时，数据通过时钟反相器进行时钟控制。 双端口锁存器被配置为接收时钟反相器的输出，第二数据位D2，时钟信号CKT和CLKZ，保持控制信号RET和RETN，预置控制信号PRE和控制信号SS和SSN。 信号CKT，CLKZ，RET，RETN，PRE，SS和SSN确定时钟反相器或第二数据位D2的输出是否锁存在双端口锁存器中。 在保留模式期间，控制信号RET和RETN确定数据是否存储在双端口锁存器中。

公开(公告)号：US20150070061A1

公开(公告)日：2015-03-12

申请号：US14447901

申请日：2014-07-31

Applicant: Texas Instruments Incorporated

Inventor： Steven C. Bartling ,  Sudhanshu Khanna

IPC: H03K3/037

CPC classification number: H03K3/0375

Abstract: In an embodiment of the invention, a dual-port negative level sensitive reset preset data retention latch contains a clocked inverter and a dual-port latch. Data is clocked through the clocked inverter when clock signal CKT goes high, CLKZ goes low, preset control signal PRE is low, rest control signal REN is high and retention control signal RET is low. The dual-port latch is configured to receive the output of the clocked inverter, a second data bit D2, the clock signals CKT and CLKZ, the retain control signals RET and RETN, the preset control signal PRE and the control signals SS and SSN. The signals CKT, CLKZ, RET, RETN, PRE, REN, SS and SSN determine whether the output of the clocked inverter or the second data bit D2 is latched in the dual-port latch. Control signals RET and RETN determine when data is stored in the dual-port latch during retention mode.

Abstract translation: 在本发明的一个实施例中，双端口负电平敏感复位预设数据保持锁存器包括时钟反相器和双端口锁存器。 当时钟信号CKT变高，CLKZ变为低电平，预置控制信号PRE为低电平，静止控制信号REN为高电平，保持控制信号RET为低电平时，数据由时钟反相器提供时钟。 双端口锁存器被配置为接收时钟反相器的输出，第二数据位D2，时钟信号CKT和CLKZ，保持控制信号RET和RETN，预置控制信号PRE和控制信号SS和SSN。 信号CKT，CLKZ，RET，RETN，PRE，REN，SS和SSN确定时钟反相器或第二数据位D2的输出是否锁存在双端口锁存器中。 在保留模式期间，控制信号RET和RETN确定数据是否存储在双端口锁存器中。

公开(公告)号：US20150054545A1

公开(公告)日：2015-02-26

申请号：US14080183

申请日：2013-11-14

Applicant: Texas Instruments Incorporated

Inventor： Steven C. Bartling ,  Sudhanshu Khanna

IPC: H03K19/173

CPC classification number: H03K19/1735 ,  H03K3/356008

Abstract: In an embodiment of the invention, a dual-port positive level sensitive reset preset data retention latch contains a clocked inverter and a dual-port latch. Data is clocked through the clocked inverter when clock signal CKT goes high, CLKZ goes low, preset control signal PRE is low, rest control signal REN is high and retention control signal RET is low. The dual-port latch is configured to receive the output of the clocked inverter, a second data bit D2, the clock signals CKT and CLKZ, the retain control signals RET and RETN, the preset control signal PRE and the control signals SS and SSN. The signals CKT, CLKZ, RET, RETN, PRE, REN, SS and SSN determine whether the output of the clocked inverter or the second data bit D2 is latched in the dual-port latch. Control signals RET and RETN determine when data is stored in the dual-port latch during retention mode.

Abstract translation: 在本发明的一个实施例中，双端口正电平敏感复位预设数据保持锁存器包括时钟反相器和双端口锁存器。 当时钟信号CKT变高，CLKZ变为低电平，预置控制信号PRE为低电平，静止控制信号REN为高电平，保持控制信号RET为低电平时，数据由时钟反相器提供时钟。 双端口锁存器被配置为接收时钟反相器的输出，第二数据位D2，时钟信号CKT和CLKZ，保持控制信号RET和RETN，预置控制信号PRE和控制信号SS和SSN。 信号CKT，CLKZ，RET，RETN，PRE，REN，SS和SSN确定时钟反相器或第二数据位D2的输出是否锁存在双端口锁存器中。 在保留模式期间，控制信号RET和RETN确定数据是否存储在双端口锁存器中。

公开(公告)号：US10734978B2

公开(公告)日：2020-08-04

申请号：US16236330

申请日：2018-12-28

Applicant: Texas Instruments Incorporated

Inventor： Soman Purushothaman ,  Sankar Prasad Debnath ,  Per Torstein Roine ,  Steven C. Bartling ,  Keshav Bhaktavatson Chintamani

IPC: H03K3/037 ,  H03K3/012

Abstract: In described examples, a latch includes circuitry for latching input information. The circuitry can be precharged in response to an indication of a first mode and can latch the input information to an indication of a second mode. The latch can optionally further latch the input information in response to a node for storing the latched input information.

公开(公告)号：US20190162590A1

公开(公告)日：2019-05-30

申请号：US16191430

申请日：2018-11-14

Applicant: Texas Instruments Incorporated

Inventor： Michael Zwerg ,  Sudhanshu Khanna ,  Steven C. Bartling ,  Brian Elies ,  Krishnasawamy Nagaraj ,  Wei-Yan Shih

IPC: G01H11/08

Abstract: In described examples, each node between adjacent capacitive elements of a stack of series-coupled capacitive elements is biased during a reset mode, where each of the capacitive elements includes piezoelectric material. A strain-induced voltage is generated across each of the capacitive elements. Each of the strain-induced voltages is combined to generate a piezoelectric-responsive output signal during a sensing mode at a time different from the time of the reset mode.

公开(公告)号：US09520862B2

公开(公告)日：2016-12-13

申请号：US14447901

申请日：2014-07-31

Applicant: Texas Instruments Incorporated

Inventor： Steven C. Bartling ,  Sudhanshu Khanna

IPC: H03K3/037

CPC classification number: H03K3/0375

Abstract: In an embodiment of the invention, a dual-port negative level sensitive reset preset data retention latch contains a clocked inverter and a dual-port latch. Data is clocked through the clocked inverter when clock signal CKT goes high, CLKZ goes low, preset control signal PRE is low, rest control signal REN is high and retention control signal RET is low. The dual-port latch is configured to receive the output of the clocked inverter, a second data bit D2, the clock signals CKT and CLKZ, the retain control signals RET and RETN, the preset control signal PRE and the control signals SS and SSN. The signals CKT, CLKZ, RET, RETN, PRE, REN, SS and SSN determine whether the output of the clocked inverter or the second data bit D2 is latched in the dual-port latch. Control signals RET and RETN determine when data is stored in the dual-port latch during retention mode.

Abstract translation: 在本发明的一个实施例中，双端口负电平敏感复位预设数据保持锁存器包括时钟反相器和双端口锁存器。 当时钟信号CKT变高，CLKZ变为低电平，预置控制信号PRE为低电平，静止控制信号REN为高电平，保持控制信号RET为低电平时，数据由时钟反相器提供时钟。 双端口锁存器被配置为接收时钟反相器的输出，第二数据位D2，时钟信号CKT和CLKZ，保持控制信号RET和RETN，预置控制信号PRE和控制信号SS和SSN。 信号CKT，CLKZ，RET，RETN，PRE，REN，SS和SSN确定时钟反相器或第二数据位D2的输出是否锁存在双端口锁存器中。 在保留模式期间，控制信号RET和RETN确定数据是否存储在双端口锁存器中。

公开(公告)号：US09007091B2

公开(公告)日：2015-04-14

申请号：US14080092

申请日：2013-11-14

Applicant: Texas Instruments Incorporated

Inventor： Steven C. Bartling ,  Sudhanshu Khanna

IPC: H03K19/173

CPC classification number: H03K19/1735 ,  H03K3/356008

Abstract: In an embodiment of the invention, a dual-port positive level sensitive preset data retention latch contains a clocked inverter and a dual-port latch. Data is clocked through the clocked inverter when clock signal CKT goes high, CLKZ goes low, preset control signal PRE is low and retention control signal RET is low. The dual-port latch is configured to receive the output of the clocked inverter, a second data bit D2, the clock signals CKT and CLKZ, the retain control signals RET and RETN, the preset control signal PRE and the control signals SS and SSN. The signals CKT, CLKZ, RET, RETN, PRE, SS and SSN determine whether the output of the clocked inverter or the second data bit D2 is latched in the dual-port latch. Control signals RET and RETN determine when data is stored in the dual-port latch during retention mode.

Abstract translation: 在本发明的实施例中，双端口正电平敏感预设数据保持锁存器包括时钟反相器和双端口锁存器。 当时钟信号CKT变高，CLKZ变为低电平，预置控制信号PRE为低电平，保持控制信号RET为低电平时，数据由时钟反相器提供时钟。 双端口锁存器被配置为接收时钟反相器的输出，第二数据位D2，时钟信号CKT和CLKZ，保持控制信号RET和RETN，预置控制信号PRE和控制信号SS和SSN。 信号CKT，CLKZ，RET，RETN，PRE，SS和SSN确定时钟反相器或第二数据位D2的输出是否锁存在双端口锁存器中。 在保留模式期间，控制信号RET和RETN确定数据是否存储在双端口锁存器中。

公开(公告)号：US12072229B2

公开(公告)日：2024-08-27

申请号：US17462090

申请日：2021-08-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Michael Zwerg ,  Sudhanshu Khanna ,  Steven C. Bartling ,  Brian Elies ,  Krishnasawamy Nagaraj ,  Wei-Yan Shih

IPC: G01H11/08

CPC classification number: G01H11/08

Abstract: In described examples, each node between adjacent capacitive elements of a stack of series-coupled capacitive elements is biased during a reset mode, where each of the capacitive elements includes piezoelectric material. A strain-induced voltage is generated across each of the capacitive elements. Each of the strain-induced voltages is combined to generate a piezoelectric-responsive output signal during a sensing mode at a time different from the time of the reset mode.

公开(公告)号：US20210389174A1

公开(公告)日：2021-12-16

申请号：US17462090

申请日：2021-08-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Michael Zwerg ,  Sudhanshu Khanna ,  Steven C. Bartling ,  Brian Elies ,  Krishnasawamy Nagaraj ,  Wei-Yan Shih

IPC: G01H11/08

Abstract: In described examples, each node between adjacent capacitive elements of a stack of series-coupled capacitive elements is biased during a reset mode, where each of the capacitive elements includes piezoelectric material. A strain-induced voltage is generated across each of the capacitive elements. Each of the strain-induced voltages is combined to generate a piezoelectric-responsive output signal during a sensing mode at a time different from the time of the reset mode.