公开(公告)号：US20230315661A1

公开(公告)日：2023-10-05

申请号：US18129665

申请日：2023-03-31

Applicant: Texas Instruments Incorporated

Inventor： Michael Zwerg

IPC: G06F13/28 ,  G06F13/16 ,  G06F12/02

CPC classification number: G06F13/28 ,  G06F13/1673 ,  G06F12/0238

Abstract: An example apparatus includes a first memory configured to store a table, and a direct memory access controller coupled to the first memory and including a second memory local to the direct memory access controller, the direct memory access controller configured to read a first set of data from a first location in the table, wherein the first set of data includes an address, write the first set of data from the table to the second memory of the direct memory access controller, read a second set of data from a second location in the table, the second location different than the first location, and write the second set of data to a third location in the first memory, wherein the third location corresponds to the address of the first set of data.

公开(公告)号：US20230315142A1

公开(公告)日：2023-10-05

申请号：US18129674

申请日：2023-03-31

Applicant: Texas Instruments Incorporated

Inventor： Michael Zwerg

IPC: G06F1/08 ,  G06F1/10

CPC classification number: G06F1/08 ,  G06F1/10

Abstract: An example apparatus includes an input terminal; an output terminal; a delay circuit including an input terminal and an output terminal, the input terminal coupled of the delay circuit coupled to the input terminal; a comparator including a first input terminal, a second input terminal, and an output terminal, the first input terminal of the comparator coupled to a supply voltage terminal, the second input terminal of the comparator coupled to a reference voltage terminal; and a logic AND gate including a first input terminal, a second input terminal, a third input terminal, and an output terminal, the first input terminal of the logic AND gate coupled to the output terminal of the comparator, the second input terminal of the logic AND gate coupled to the output terminal of the delay circuit, the third input terminal of the logic AND gate coupled to the input terminal, and the output terminal of the logic AND gate coupled to the output terminal.

公开(公告)号：US20210373647A1

公开(公告)日：2021-12-02

申请号：US17404125

申请日：2021-08-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Michael Zwerg ,  Steven Craig Bartling ,  Sudhanshu Khanna

IPC: G06F1/3293 ,  G06F3/06 ,  G06F1/3206 ,  G06F1/3287 ,  G06F11/07

Abstract: A computing device apparatus facilitates use of a deep low power mode that includes powering off the device's CPU by including a hardware implemented process to trigger storage of data from the device's volatile storage elements in non-volatile memory in response to entering the low power mode. A hardware based power management unit controls the process including interrupting a normal processing order of the CPU and triggering the storage of the data in the non-volatile memory. In response to a wake-up event, the device is triggered to restore the data stored in the non-volatile memory to the volatile memory prior to execution of a wake up process for the CPU from the low power mode. The device includes a power storage element such as a capacitor that holds sufficient energy to complete the non-volatile data storage task prior to entering the low power mode.

公开(公告)号：US20240385924A1

公开(公告)日：2024-11-21

申请号：US18345449

申请日：2023-06-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Michael Zwerg ,  Gregory North ,  Ashwini Gopinath

IPC: G06F11/10 ,  G06F12/02 ,  G06F13/28

Abstract: Various examples disclosed herein relate to trimming of system elements to prepare the elements for execution of boot code and application code. In an example embodiment, a system is provided. The system includes system control circuitry, direct memory access (DMA) circuitry, and processing circuitry. The system control circuitry is configured to instruct the DMA circuitry to obtain trim data from memory upon detecting that a first group of system elements has reached an initialized state. The DMA circuitry obtains the trim data and writes it to trim registers. The system control circuitry supplies the trim data to a second group of system elements to bring them to an operational level, then instructs the processing circuitry to execute boot code.

公开(公告)号：US10545728B2

公开(公告)日：2020-01-28

申请号：US15828204

申请日：2017-11-30

Applicant: Texas Instruments Incorporated

Inventor： Sudhanshu Khanna ,  Hao Meng ,  Michael Zwerg ,  Christy Leigh She ,  Steven Craig Bartling

IPC: H03K21/00 ,  G06F7/62 ,  G06F1/26 ,  G08C13/02 ,  H03K5/24 ,  H03K21/40 ,  G11C11/56

Abstract: Disclosed examples include non-volatile counter systems to generate and store a counter value according to a sensor pulse signal, and power circuits to generate first and second supply voltage signals to power first and second power domain circuits using power from the sensor pulse signal, including a switch connected between first and second power domain supply nodes, a boost circuit, and a control circuit to selectively cause the switch to disconnect the first and second power domain circuits from one another after the first supply voltage signal rises above a threshold voltage in a given pulse of the sensor pulse signal, and to cause the boost circuit to boost the second supply voltage signal after the regulator output is disconnected from the second power domain supply node in the given pulse.

公开(公告)号：US10331203B2

公开(公告)日：2019-06-25

申请号：US15016449

申请日：2016-02-05

Applicant: Texas Instruments Incorporated

Inventor： Michael Zwerg ,  Steven Craig Bartling ,  Sudhanshu Khanna

IPC: G06F1/3293 ,  G06F1/3287 ,  G06F3/06 ,  G06F11/07 ,  G06F1/3206

Abstract: A computing device apparatus facilitates use of a deep low power mode that includes powering off the device's CPU by including a hardware implemented process to trigger storage of data from the device's volatile storage elements in non-volatile memory in response to entering the low power mode. A hardware based power management unit controls the process including interrupting a normal processing order of the CPU and triggering the storage of the data in the non-volatile memory. In response to a wake-up event, the device is triggered to restore the data stored in the non-volatile memory to the volatile memory prior to execution of a wake up process for the CPU from the low power mode. The device includes a power storage element such as a capacitor that holds sufficient energy to complete the non-volatile data storage task prior to entering the low power mode.

公开(公告)号：US20170185139A1

公开(公告)日：2017-06-29

申请号：US15016449

申请日：2016-02-05

Applicant: Texas Instruments Incorporated

Inventor： Michael Zwerg ,  Steven Craig Bartling ,  Sudhanshu Khanna

IPC: G06F1/32 ,  G06F3/06

CPC classification number: G06F1/3293 ,  G06F1/3206 ,  G06F1/3287 ,  G06F3/061 ,  G06F3/0625 ,  G06F3/0634 ,  G06F3/0655 ,  G06F3/0656 ,  G06F3/0688 ,  Y02D10/154 ,  Y02D10/171 ,  Y02D50/20

Abstract: A computing device apparatus facilitates use of a deep low power mode that includes powering off the device's CPU by including a hardware implemented process to trigger storage of data from the device's volatile storage elements in non-volatile memory in response to entering the low power mode. A hardware based power management unit controls the process including interrupting a normal processing order of the CPU and triggering the storage of the data in the non-volatile memory. In response to a wake-up event, the device is triggered to restore the data stored in the non-volatile memory to the volatile memory prior to execution of a wake up process for the CPU from the low power mode. The device includes a power storage element such as a capacitor that holds sufficient energy to complete the non-volatile data storage task prior to entering the low power mode.

公开(公告)号：US12222747B2

公开(公告)日：2025-02-11

申请号：US18129674

申请日：2023-03-31

Applicant: Texas Instruments Incorporated

Inventor： Michael Zwerg

IPC: G06F1/00 ,  G06F1/08 ,  G06F1/10

Abstract: An example apparatus includes an input terminal; an output terminal; a delay circuit including an input terminal and an output terminal, the input terminal coupled of the delay circuit coupled to the input terminal; a comparator including a first input terminal, a second input terminal, and an output terminal, the first input terminal of the comparator coupled to a supply voltage terminal, the second input terminal of the comparator coupled to a reference voltage terminal; and a logic AND gate including a first input terminal, a second input terminal, a third input terminal, and an output terminal, the first input terminal of the logic AND gate coupled to the output terminal of the comparator, the second input terminal of the logic AND gate coupled to the output terminal of the delay circuit, the third input terminal of the logic AND gate coupled to the input terminal, and the output terminal of the logic AND gate coupled to the output terminal.

公开(公告)号：US20240281394A1

公开(公告)日：2024-08-22

申请号：US18458369

申请日：2023-08-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Michael Zwerg

IPC: G06F13/28

CPC classification number: G06F13/28

Abstract: Various embodiments disclosed herein relate to an event manager for handling event notification and acknowledgement between circuits in a computing device. The event manager may be configured with static channels, direct memory access (DMA) channels, and dynamically configured channels. Each of the channels has conductors that allow a publishing circuit to assert a request signal on a conductor to notify the subscribing circuit of an event and the subscribing circuit to assert an acknowledge signal on a second conductor to notify the publishing circuit of receipt of the request signal. Using the request and acknowledge signals, the publishing circuit and subscribing circuit can engage in a 4-way handshake that ensures no events are lost and the events can be communicated reliably across clock domains.

公开(公告)号：US11132050B2

公开(公告)日：2021-09-28

申请号：US16451260

申请日：2019-06-25

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Michael Zwerg ,  Steven Craig Bartling ,  Sudhanshu Khanna

IPC: G06F1/3293 ,  G06F3/06 ,  G06F1/3206 ,  G06F1/3287 ,  G06F11/07

Abstract: A computing device apparatus facilitates use of a deep low power mode that includes powering off the device's CPU by including a hardware implemented process to trigger storage of data from the device's volatile storage elements in non-volatile memory in response to entering the low power mode. A hardware based power management unit controls the process including interrupting a normal processing order of the CPU and triggering the storage of the data in the non-volatile memory. In response to a wake-up event, the device is triggered to restore the data stored in the non-volatile memory to the volatile memory prior to execution of a wake up process for the CPU from the low power mode. The device includes a power storage element such as a capacitor that holds sufficient energy to complete the non-volatile data storage task prior to entering the low power mode.