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公开(公告)号:US11444012B2
公开(公告)日:2022-09-13
申请号:US16831503
申请日:2020-03-26
Applicant: Texas Instruments Incorporated
Inventor: Yuh-Harng Chien , Chang-Yen Ko , Chih-Chien Ho
Abstract: In a described example, an apparatus includes a package substrate with a split die pad having a slot between a die mount portion and a wire bonding portion; a first end of the wire bonding portion coupled to the die mount portion at one end of the slot; a second end of the wire bonding portion coupled to a first lead on the package substrate. At least one semiconductor die is mounted on the die mount portion; a first end of a first wire bond is bonded to a first bond pad on the at least one semiconductor die; a second end of the first wire bond is bonded to the wire bonding portion; and mold compound covers the at least one semiconductor die, the die mount portion, the wire bonding portion, and fills the slot.
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公开(公告)号:US10600724B2
公开(公告)日:2020-03-24
申请号:US15151177
申请日:2016-05-10
Applicant: Texas Instruments Incorporated
Inventor: Chia-Yu Chang , Chih-Chien Ho , Steven Su
IPC: H01L23/495 , G06F17/50 , H01L23/00 , H01L23/31
Abstract: A leadframe includes a first die attach pad (“DAP”) having a first longitudinally extending edge surface and a second DAP having a first longitudinally extending edge surface. The second DAP is positioned with the first longitudinally extending edge surface thereof in adjacent, laterally and vertically spaced relationship with the first longitudinally extending edge surface of the first DAP.
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公开(公告)号:US20180174950A1
公开(公告)日:2018-06-21
申请号:US15896971
申请日:2018-02-14
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Yuh-Harng Chien , Chih-Chien Ho , Steven Su
IPC: H01L23/495 , H01L25/18 , H01L23/00 , H01L23/31 , H01L23/498 , H01L25/065
CPC classification number: H01L23/49541 , H01L21/56 , H01L23/3121 , H01L23/49503 , H01L23/49551 , H01L23/49575 , H01L23/49861 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/73 , H01L25/0655 , H01L25/18 , H01L2224/05554 , H01L2224/05599 , H01L2224/2919 , H01L2224/32245 , H01L2224/45144 , H01L2224/45147 , H01L2224/48137 , H01L2224/48138 , H01L2224/49175 , H01L2224/73265 , H01L2224/85399 , H01L2924/00014 , H01L2924/0665 , H01L2924/10253 , H01L2924/10329 , H01L2924/17747
Abstract: A leadframe includes a plurality of interconnected support members. A pair of die pads is connected to the support members and configured to receive a pair of dies electrically connected by at least one wire. A support bracket extends between the die pads and includes a surface for maintaining the at least one wire at a predetermined distance from the die pads during overmolding of the leadframe.
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公开(公告)号:US09627331B1
公开(公告)日:2017-04-18
申请号:US14985127
申请日:2015-12-30
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Yuh-Harng Chien , Chih-Chien Ho , Steven Su
IPC: H01L23/00 , H01L23/495 , H01L21/48 , H01L21/56
CPC classification number: H01L23/49541 , H01L21/56 , H01L23/3121 , H01L23/49503 , H01L23/49551 , H01L23/49575 , H01L23/49861 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/73 , H01L25/0655 , H01L25/18 , H01L2224/05554 , H01L2224/2919 , H01L2224/32245 , H01L2224/45144 , H01L2224/45147 , H01L2224/48137 , H01L2224/48138 , H01L2224/49175 , H01L2224/73265 , H01L2924/00014 , H01L2924/0665 , H01L2924/10253 , H01L2924/10329 , H01L2924/17747 , H01L2224/05599 , H01L2224/85399
Abstract: A leadframe includes a plurality of interconnected support members. A pair of die pads is connected to the support members and configured to receive a pair of dies electrically connected by at least one wire. A support bracket extends between the die pads and includes a surface for maintaining the at least one wire at a predetermined distance from the die pads during overmolding of the leadframe.
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公开(公告)号:US11817374B2
公开(公告)日:2023-11-14
申请号:US17229955
申请日:2021-04-14
Applicant: Texas Instruments Incorporated
Inventor: Chih-Chien Ho , Bo-Hsun Pan , Yuh-Harng Chien
IPC: H01L23/495 , H01L21/50 , H01L21/56 , H01L23/00
CPC classification number: H01L23/4951 , H01L21/50 , H01L23/49541 , H01L23/49551 , H01L23/49575 , H01L24/49 , H01L24/85 , H01L2924/181
Abstract: A packaged electronic device has a package structure, first leads, second leads and a tie bar. The package structure has a first side, a second side, a third side, a fourth side, a fifth side and a sixth side, the second side spaced from the first side along a first direction, the fourth side spaced from the third side along an orthogonal second direction, and the sixth side spaced from the fifth side along an orthogonal third direction. The first leads extend outward in a first plane of the second and third directions from respective portions of the third side, the second leads extend outward in the first plane from respective portions of the fourth side, and the tie bar is exposed along the fifth side in a second plane of the second and third directions, the second plane between the first plane and the first side.
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公开(公告)号:US20230317571A1
公开(公告)日:2023-10-05
申请号:US17708038
申请日:2022-03-30
Applicant: Texas Instruments Incorporated
Inventor: Hsiang Ming Hsiao , Hung-Yu Chou , Yuh-Harng Chien , Chih-Chien Ho , Che Wei Tu , Bo-Hsun Pan , Megan Chang
IPC: H01L23/495 , H01L23/31 , H01L21/48 , H01L21/56
CPC classification number: H01L23/49555 , H01L21/56 , H01L21/4821 , H01L23/3107
Abstract: An electronic device with a conductive lead having an internal first section and an external second section extending outside a molded package structure, the first section having an obstruction feature extending vertically from a top or bottom side of the conductive lead and engaging a portion of the package structure to oppose movement of the conductive lead outward from the package structure.
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公开(公告)号:US20230121743A1
公开(公告)日:2023-04-20
申请号:US17504148
申请日:2021-10-18
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Chih-Chien Ho
Abstract: A method for aligning interconnects that includes trimming and forming a frame of strips of interconnects. The frame of strips of interconnects includes interdigitated pins. The method also includes removing siderails from the frame of strips of interconnects to provide an array of strips of interconnects. The method includes aligning a first set of strips of interconnects in the array of strips of interconnects such that pins of the first set of strips of interconnects are aligned with pins of a second set of strips of interconnects in the array of strips of interconnects. A strip of interconnects of the first set of strips of interconnects are adjacent to a strip of interconnects of the second set of strips of interconnects to provide an aligned array of strips of interconnects. The method further includes singulating the aligned array of strips of interconnects.
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公开(公告)号:US20210043548A1
公开(公告)日:2021-02-11
申请号:US16537535
申请日:2019-08-10
Applicant: Texas Instruments Incorporated
Inventor: Stanley Chou , Yuh-Harng Chien , Steven Alfred Kummerl , Bo-Hsun Pan , Pi-Chiang Huang , Frank Yu , Chih-Chien Ho
IPC: H01L23/495 , H01L23/492 , H01L23/00
Abstract: An electronic device includes a package structure with opposite first and second sides spaced apart along a first direction, opposite third and fourth sides spaced apart along a second direction, opposite fifth and sixth sides spaced apart along a third direction, the first, second, and third directions being orthogonal to one another. A set of first leads extend outward from the first side along the first direction, a set of second leads extend outward from the second side along the first direction, and a thermal pad includes a first portion that extends along a portion of the fifth side, and a second portion that extends along a portion of the third side to facilitate cooling and visual solder inspection when soldered to a host printed circuit board.
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公开(公告)号:US20220336331A1
公开(公告)日:2022-10-20
申请号:US17229955
申请日:2021-04-14
Applicant: Texas Instruments Incorporated
Inventor: Chih-Chien Ho , Bo-Hsun Pan , Yuh-Harng Chien
IPC: H01L23/495 , H01L21/50
Abstract: A packaged electronic device has a package structure, first leads, second leads and a tie bar. The package structure has a first side, a second side, a third side, a fourth side, a fifth side and a sixth side, the second side spaced from the first side along a first direction, the fourth side spaced from the third side along an orthogonal second direction, and the sixth side spaced from the fifth side along an orthogonal third direction. The first leads extend outward in a first plane of the second and third directions from respective portions of the third side, the second leads extend outward in the first plane from respective portions of the fourth side, and the tie bar is exposed along the fifth side in a second plane of the second and third directions, the second plane between the first plane and the first side.
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公开(公告)号:US20210305139A1
公开(公告)日:2021-09-30
申请号:US16831503
申请日:2020-03-26
Applicant: Texas Instruments Incorporated
Inventor: Yuh-Harng Chien , Chang-Yen Ko , Chih-Chien Ho
Abstract: In a described example, an apparatus includes a package substrate with a split die pad having a slot between a die mount portion and a wire bonding portion; a first end of the wire bonding portion coupled to the die mount portion at one end of the slot; a second end of the wire bonding portion coupled to a first lead on the package substrate. At least one semiconductor die is mounted on the die mount portion; a first end of a first wire bond is bonded to a first bond pad on the at least one semiconductor die; a second end of the first wire bond is bonded to the wire bonding portion; and mold compound covers the at least one semiconductor die, the die mount portion, the wire bonding portion, and fills the slot.
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