公开(公告)号：US20240120367A1

公开(公告)日：2024-04-11

申请号：US18390395

申请日：2023-12-20

Applicant: Texas Instruments Incorporated

Inventor： Elizabeth Costner Stewart ,  Thomas Dyer Bonifield ,  Jeffrey Alan West ,  Byron Lovell Williams

IPC: H01G4/30 ,  H01L23/00 ,  H01L23/495 ,  H01L25/16

CPC classification number: H01L28/60 ,  H01L23/49575 ,  H01L24/05 ,  H01L25/16 ,  H01L2224/0556 ,  H01L2224/05624

Abstract: An electronic device includes a first dielectric layer above a semiconductor layer, lower-bandgap dielectric layer above the first dielectric layer, the lower-bandgap dielectric layer having a bandgap energy less than a bandgap energy of the first dielectric layer, a first capacitor plate above the lower-bandgap dielectric layer in a first plane of first and second directions, a second dielectric layer above the first capacitor plate, a second capacitor plate above the second dielectric layer in a second plane of the first and second directions, the first and second capacitor plates spaced apart from one another along a third direction, and a conductive third capacitor plate above the second dielectric layer in the second plane, the third capacitor plate spaced apart from the second capacitor plate in the second plane.

公开(公告)号：US20230056046A1

公开(公告)日：2023-02-23

申请号：US17682762

申请日：2022-02-28

Applicant: Texas Instruments Incorporated

Inventor： Byron Lovell Williams ,  Elizabeth Costner Stewart ,  Jeffrey Alan West ,  Thomas Dyer Bonifield

IPC: H01L23/522 ,  H01L23/528 ,  H01L21/768

Abstract: An electronic device has a conductive shield between first and second regions in a multilevel metallization structure, as well as a capacitor with first and second terminals in the first region, the first terminal laterally overlaps the second terminal by an overlap distance of 1.0 μm to 6.0 μm, the conductive shield includes a first metal line that encircles the first terminal, and the first metal line is spaced apart from the first terminal by a gap distance of 0.5 μm to 1.0 μm.

公开(公告)号：US11139227B2

公开(公告)日：2021-10-05

申请号：US16806362

申请日：2020-03-02

Applicant: Texas Instruments Incorporated

Inventor： Thomas Dyer Bonifield

IPC: H01L23/498 ,  H01L23/64 ,  H01L25/065 ,  H01L49/02 ,  H01L21/48 ,  H01L23/00 ,  H01L25/00

Abstract: An isolator device includes a laminate die having a dielectric laminate material with a metal laminate layer on one side of the dielectric laminate material, the metal laminate layer being a patterned layer providing at least a first plate, including a dielectric layer over the first plate that includes an aperture exposing a portion of the first plate. An integrated circuit (IC) including a substrate having a semiconductor surface includes circuitry including a transmitter and/or a receiver, the IC including a top metal layer providing at least a second plate coupled to a node in the circuitry, with at least one passivation layer on the top metal layer. A non-conductive die attach (NCDA) material for attaching a side of the dielectric laminate material is opposite the metal laminate layer to the IC so that the first plate is at least partially over the second plate to provide a capacitor.

公开(公告)号：US11024576B1

公开(公告)日：2021-06-01

申请号：US16732296

申请日：2019-12-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jeffrey Alan West ,  Byron Lovell Williams ,  Thomas Dyer Bonifield

IPC: H01L23/522 ,  H01L23/498 ,  H01L43/04 ,  H01L21/48 ,  H01L21/56

Abstract: A semiconductor package includes a leadframe including a sensor coil between sensor coil leads and further including a plurality of die leads physically and electrically separated from the sensor coil, and a semiconductor die over the leadframe with die contacts electrically connected to the die leads. The semiconductor die includes a sensor operable to detect magnetic fields created by electrical current through the sensor coil, the semiconductor die operable to output a signal representative of the detected magnetic fields via the die leads. The semiconductor package further includes a dielectric underfill filling a gap between the sensor coil and the semiconductor die, and a dielectric mold compound covering the sensor coil and the dielectric underfill and at least partially covering the semiconductor die and the die leads.

公开(公告)号：US10705159B2

公开(公告)日：2020-07-07

申请号：US16502317

申请日：2019-07-03

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Erika Lynn Mazotti ,  Dok Won Lee ,  William David French ,  Byron J R Shulver ,  Thomas Dyer Bonifield ,  Ricky Alan Jackson ,  Neil Gibson

IPC: G01R33/04 ,  G01R33/00

Abstract: An integrated fluxgate device has a magnetic core disposed over a semiconductor substrate. A first winding is disposed in a first metallization level above and a second metallization level below the magnetic core, and is configured to generate a first magnetic field in the magnetic core. A second winding is disposed in the first and second metallization levels and is configured to generate a second magnetic field in the magnetic core. A third winding is disposed in the first and second metallization levels and is configured to sense a magnetic field in the magnetic core that is the net of the first and second magnetic fields.

公开(公告)号：US10345397B2

公开(公告)日：2019-07-09

申请号：US15169639

申请日：2016-05-31

Applicant: Texas Instruments Incorporated

Inventor： Erika Lynn Mazotti ,  Dok Won Lee ,  William David French ,  Byron J R Shulver ,  Thomas Dyer Bonifield ,  Ricky Alan Jackson ,  Neil Gibson

IPC: G01R33/04 ,  G01R33/00

Abstract: An integrated fluxgate device has a magnetic core on a control circuit. The magnetic core has a volume and internal structure sufficient to have low magnetic noise and low non-linearity. A stress control structure is disposed proximate to the magnetic core. An excitation winding, a sense winding and a compensation winding are disposed around the magnetic core. An excitation circuit disposed in the control circuit is coupled to the excitation winding, configured to provide current at high frequency to the excitation winding sufficient to generate a saturating magnetic field in the magnetic core during each cycle at the high frequency. An isolation structure is disposed between the magnetic core and the windings, sufficient to enable operation of the excitation winding and the sense winding at the high frequency at low power.

公开(公告)号：US20240274529A1

公开(公告)日：2024-08-15

申请号：US18641739

申请日：2024-04-22

Applicant: Texas Instruments Incorporated

Inventor： Klaas De Haan ,  Mikhail Valeryevich Ivanov ,  Tobias Bernhard Fritz ,  Swaminathan Sankaran ,  Thomas Dyer Bonifield

IPC: H01L23/522 ,  H01L21/50 ,  H01L23/50 ,  H04L25/02

CPC classification number: H01L23/5227 ,  H01L21/50 ,  H01L23/50 ,  H01L23/5222 ,  H04L25/0268

Abstract: An electronic device has an electronic device includes a substrate and a first dielectric layer over the substrate. The electronic device also includes a first metal layer on the first dielectric layer, the first metal layer including a first plate and a second dielectric layer over the first dielectric layer and the first metal layer. Additionally, the electronic device includes a second metal layer on the second dielectric layer. The second metal layer includes a second plate spaced apart from the first plate and a winding around the second plate.

公开(公告)号：US20240113042A1

公开(公告)日：2024-04-04

申请号：US17958040

申请日：2022-09-30

Applicant: Texas Instruments Incorporated

Inventor： Jeffrey Alan West ,  Thomas Dyer Bonifield ,  Toshiyuki Tamura ,  Yoshihiro Takei

IPC: H01L23/58 ,  H01L21/762 ,  H01L23/00 ,  H01L23/532 ,  H01L23/544

CPC classification number: H01L23/585 ,  H01L21/762 ,  H01L23/53295 ,  H01L23/544 ,  H01L24/06 ,  H01L2223/54426 ,  H01L2224/04042 ,  H01L2224/06102

Abstract: A microelectronic device including an isolation device. The isolation device includes a lower isolation element, an upper isolation element, and an inorganic dielectric plateau between the lower isolation element and the upper isolation element. The inorganic dielectric plateau contains an upper etch stop layer and a lower etch stop layer between the upper isolation element and the lower isolation element. The upper etch stop layer provides an end point signal during the plateau etch process which provides feedback on the amount of inorganic dielectric plateau which has been etched. The lower etch stop layer provides a traditional etch stop function to provide for a complete plateau etch and protection of an underlying metal bond pad. The inorganic dielectric plateau also contains alternating layers of high stress and low stress silicon dioxide, which provide a means of reinforcement of the inorganic dielectric plateau.

公开(公告)号：US11901402B2

公开(公告)日：2024-02-13

申请号：US17529750

申请日：2021-11-18

Applicant: Texas Instruments Incorporated

Inventor： Elizabeth Costner Stewart ,  Thomas Dyer Bonifield ,  Jeffrey Alan West ,  Byron Lovell Williams

IPC: H01L23/00 ,  H01L23/495 ,  H01L25/16 ,  H01L49/02

CPC classification number: H01L28/60 ,  H01L23/49575 ,  H01L24/05 ,  H01L25/16 ,  H01L2224/0556 ,  H01L2224/05624

Abstract: An electronic device includes a first dielectric layer above a semiconductor layer, lower-bandgap dielectric layer above the first dielectric layer, the lower-bandgap dielectric layer having a bandgap energy less than a bandgap energy of the first dielectric layer, a first capacitor plate above the lower-bandgap dielectric layer in a first plane of first and second directions, a second dielectric layer above the first capacitor plate, a second capacitor plate above the second dielectric layer in a second plane of the first and second directions, the first and second capacitor plates spaced apart from one another along a third direction, and a conductive third capacitor plate above the second dielectric layer in the second plane, the third capacitor plate spaced apart from the second capacitor plate in the second plane.

公开(公告)号：US20230420489A1

公开(公告)日：2023-12-28

申请号：US18242717

申请日：2023-09-06

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Thomas Dyer Bonifield ,  Jeffrey Alan West ,  Byron Lovell Williams ,  Elizabeth Costner Stewart

IPC: H01G4/005 ,  H01L27/02 ,  H01L23/522

CPC classification number: H01L28/60 ,  H01L23/5223 ,  H01L27/0292

Abstract: A galvanic isolation capacitor device includes a semiconductor substrate and a PMD layer over the semiconductor substrate. The PMD layer has a first thickness. A lower metal plate is over the PMD layer and an ILD layer is on the lower metal plate; the ILD layer has a second thickness. A ratio of the first thickness to the second thickness is between about 1 and 1.55 inclusive. A first upper metal plate over the ILD layer has a first area and a second upper metal plate over the ILD layer has a second area; a ratio of the first area to the second area is greater than about 5. The galvanic isolation capacitor device can be part of a multi-chip module.