Controlled slew rate current limited ramp down voltage control

    公开(公告)号:US11616438B2

    公开(公告)日:2023-03-28

    申请号:US16724218

    申请日:2019-12-21

    Abstract: A power circuit includes a switch circuit, an auxiliary load circuit coupled to an output terminal, a switching control circuit to operate the switch circuit responsive to an error signal, a regulator circuit having a sense resistor, a comparator to provide the error signal, and a DAC to control a sense current of the sense resistor. A DAC control circuit provides a DAC input signal having a controlled ramp rate responsive to a decreasing setpoint signal, a load control circuit selectively enables the auxiliary load circuit responsive to the decreasing setpoint signal and responsive to the error signal to control the power circuit slew rate.

    Self-learning and self-correcting decoding of BMC encoded signal

    公开(公告)号:US09621304B2

    公开(公告)日:2017-04-11

    申请号:US14788147

    申请日:2015-06-30

    CPC classification number: H04L1/0046 H03M5/12 H03M13/151 H04L25/4904

    Abstract: A method of decoding a biphase mark coded (BMC) data stream. A BMC encoded signal (BMC signal) including a preamble and data payload is received at a receiver which includes a BMC decoder state machine (state machine). The preamble is processed using the state machine including measuring a total duration spanning at least three transitions to provide a ≧2 UI duration measure, a calculated 0.75 UI duration value (0.75 UI duration value) is generated from the ≧2 UI duration measure, and the 0.75 UI duration value is compared to a programmed UI range. Provided the 0.75 UI duration value is within the programmed UI range data, respective bits are extracted bit-by-bit from the data payload using the 0.75 UI duration value to obtain unencoded data.

    DIGITAL BUS ACTIVITY MONITOR
    5.
    发明申请

    公开(公告)号:US20220391337A1

    公开(公告)日:2022-12-08

    申请号:US17888687

    申请日:2022-08-16

    Abstract: One example relates to a device that includes an activity monitor. The activity monitor includes a bus interface having inputs coupled to receive signals from a bus and having outputs coupled to provide signals to an other device. The activity monitor monitors the bus for a message directed to a predefined address that is associated with the other device in response to detecting that the other device is a low power sleep mode, the activity monitor outputs the predefined address to the other device to enable the other device to capture the predefined address, via the bus interface, in response to the monitored address matching the predefined address that is associated with the other device.

    Digital bus activity monitor
    6.
    发明授权

    公开(公告)号:US11436170B2

    公开(公告)日:2022-09-06

    申请号:US16865606

    申请日:2020-05-04

    Abstract: One example relates to a device that includes an activity monitor. The activity monitor includes a bus interface having inputs coupled to receive signals from a bus and having outputs coupled to provide signals to an other device. The activity monitor monitors the bus for a message directed to a predefined address that is associated with the other device in response to detecting that the other device is a low power sleep mode, the activity monitor outputs the predefined address to the other device to enable the other device to capture the predefined address, via the bus interface, in response to the monitored address matching the predefined address that is associated with the other device.

    Digital bus activity monitor
    7.
    发明授权

    公开(公告)号:US10664424B2

    公开(公告)日:2020-05-26

    申请号:US15801653

    申请日:2017-11-02

    Abstract: One example relates to a device that includes an activity monitor. The activity monitor includes a bus interface having inputs coupled to receive signals from a bus and having outputs coupled to provide signals to an other device. The activity monitor monitors the bus for a message directed to a predefined address that is associated with the other device in response to detecting that the other device is a low power sleep mode, the activity monitor outputs the predefined address to the other device to enable the other device to capture the predefined address, via the bus interface, in response to the monitored address matching the predefined address that is associated with the other device.

    Waveform synthesizer using multiple digital-to-analog converters

    公开(公告)号:US11265009B2

    公开(公告)日:2022-03-01

    申请号:US16730612

    申请日:2019-12-30

    Abstract: A circuit includes a phase-locked loop having a phase-locked loop output to provide a first phase signal and a second phase signal phase delayed with respect to the first phase signal. The circuit further includes a digital circuit having a digital circuit input and an output. The digital circuit input couples to the phase-locked loop output. On the digital circuit output, the digital circuit is configured to provide a first digital-to-analog converter (DAC) enable signal and a second DAC enable signal. The circuit also includes first and second DACs. The first DAC is coupled to the digital circuit. The first DAC has a first enable input coupled to the digital circuit output to receive the first DAC enable signal. The second DAC is coupled to the digital circuit. The second DAC has a second enable input coupled to the digital circuit output to receive the second DAC enable signal.

    CONTROLLED SLEW RATE CURRENT LIMITED RAMP DOWN VOLTAGE CONTROL

    公开(公告)号:US20210194362A1

    公开(公告)日:2021-06-24

    申请号:US16724218

    申请日:2019-12-21

    Abstract: A power circuit includes a switch circuit, an auxiliary load circuit coupled to an output terminal, a switching control circuit to operate the switch circuit responsive to an error signal, a regulator circuit having a sense resistor, a comparator to provide the error signal, and a DAC to control a sense current of the sense resistor. A DAC control circuit provides a DAC input signal having a controlled ramp rate responsive to a decreasing setpoint signal, a load control circuit selectively enables the auxiliary load circuit responsive to the decreasing setpoint signal and responsive to the error signal to control the power circuit slew rate.

    DIGITAL BUS ACTIVITY MONITOR
    10.
    发明申请

    公开(公告)号:US20200334182A1

    公开(公告)日:2020-10-22

    申请号:US16865606

    申请日:2020-05-04

    Abstract: One example relates to a device that includes an activity monitor. The activity monitor includes a bus interface having inputs coupled to receive signals from a bus and having outputs coupled to provide signals to an other device. The activity monitor monitors the bus for a message directed to a predefined address that is associated with the other device in response to detecting that the other device is a low power sleep mode, the activity monitor outputs the predefined address to the other device to enable the other device to capture the predefined address, via the bus interface, in response to the monitored address matching the predefined address that is associated with the other device.

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