公开(公告)号：US20250076945A1

公开(公告)日：2025-03-06

申请号：US18498757

申请日：2023-10-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Ruchi Shankar ,  Robin O. Hoel ,  Patrick Seem ,  Oddgeir Fikstvedt ,  Jan-Tore Marienborg

IPC: G06F1/26 ,  G06F1/3203 ,  H03K3/356 ,  H03K19/0185

Abstract: Embodiments disclosed herein relate to split rail architecture for power supplies in a system, and more particularly, to providing isolation and control of a power supply. In an example, an integrated circuit device is provided that includes a device voltage supply, an input/output (I/O) voltage supply coupled to the device voltage supply, and a level shifter circuit coupled to the I/O voltage supply. The level shifter circuit includes a pair of cross-coupled p-type metal-oxide semiconductor field effect transistors (PMOS transistors), a pair of n-type transistors (NMOS transistors) coupled between the pair of cross-coupled PMOS transistors and a ground connection, and an inverter circuit coupled to the device voltage supply and the level shifter circuit. The level shifter circuit further includes a capacitor coupled to the pair of cross-coupled PMOS transistors and the ground connection and is in parallel with respect to a first one of the pair of NMOS transistors.

公开(公告)号：US09240801B2

公开(公告)日：2016-01-19

申请号：US14211233

申请日：2014-03-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jan-Tore Marienborg ,  Gregory Arndt ,  Stefan Dannenberger

IPC: H03M3/00 ,  H03M1/00 ,  H03M1/12

CPC classification number: H03M3/424 ,  H03M1/00 ,  H03M1/12 ,  H03M1/56 ,  H03M1/822 ,  H03M3/30 ,  H03M3/438

Abstract: A delta sigma analog-to-digital converter (ADC) providing optimized performance and energy consumption. In one embodiment, a delta-sigma ADC includes a loop filter and a multi-bit quantizer. The multi-bit quantizer is coupled to the loop filter. The quantizer includes a counter, a reference voltage generator, and a comparator. The counter is configured to provide a multi-bit output value that estimates an output of the loop filter. The reference voltage generator is configured to generate a reference voltage ramp based on the output value of the counter. The comparator is coupled to the reference voltage generator to compare the reference voltage ramp to output of the loop filter.

Abstract translation: 提供优化的性能和能耗的Δ-Σ模数转换器（ADC）。 在一个实施例中，Δ-ΣADC包括环路滤波器和多位量化器。 多位量化器耦合到环路滤波器。 量化器包括计数器，参考电压发生器和比较器。 计数器被配置为提供估计环路滤波器的输出的多位输出值。 参考电压发生器被配置为基于计数器的输出值产生参考电压斜坡。 比较器耦合到参考电压发生器，以将参考电压斜坡与环路滤波器的输出进行比较。

公开(公告)号：US09735802B1

公开(公告)日：2017-08-15

申请号：US15367667

申请日：2016-12-02

Applicant: Texas Instruments Incorporated

Inventor： Jan-Tore Marienborg ,  Tobias Edström

IPC: H03M1/06 ,  H03M3/00 ,  H03M1/12 ,  H03M1/10

CPC classification number: H03M3/422 ,  H03M1/0617 ,  H03M1/1009 ,  H03M1/1245 ,  H03M3/368 ,  H03M3/412 ,  H03M3/454 ,  H03M3/458 ,  H03M3/49

Abstract: A voltage-controlled oscillator-based delta-sigma analog-to-digital converter (VCO-based ΔΣ ADC) includes a VCO-based quantizer that includes delay elements to provide VCO outputs based on an analog input signal and combining logic to combine the VCO outputs so as to provide quantized outputs. Detection logic detects saturation of the VCO-based quantizer based on the quantized outputs and at least a portion of the VCO outputs. The VCO-based ΔΣ ADC also includes correction logic to modify the quantized outputs and provide modified quantized outputs in response to the detection logic detecting the saturation of the VCO-based quantizer and to provide the quantized outputs unmodified in the absence of saturation being detected.

公开(公告)号：US20150263759A1

公开(公告)日：2015-09-17

申请号：US14211233

申请日：2014-03-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jan-Tore Marienborg ,  Gregory Arndt ,  Stefan Dannenberger

IPC: H03M3/00

CPC classification number: H03M3/424 ,  H03M1/00 ,  H03M1/12 ,  H03M1/56 ,  H03M1/822 ,  H03M3/30 ,  H03M3/438

Abstract: A delta sigma analog-to-digital converter (ADC) providing optimized performance and energy consumption. In one embodiment, a delta-sigma ADC includes a loop filter and a multi-bit quantizer. The multi-bit quantizer is coupled to the loop filter. The quantizer includes a counter, a reference voltage generator, and a comparator. The counter is configured to provide a multi-bit output value that estimates an output of the loop filter. The reference voltage generator is configured to generate a reference voltage ramp based on the output value of the counter. The comparator is coupled to the reference voltage generator to compare the reference voltage ramp to output of the loop filter.

Abstract translation: 提供优化的性能和能耗的Δ-Σ模数转换器（ADC）。 在一个实施例中，Δ-ΣADC包括环路滤波器和多位量化器。 多位量化器耦合到环路滤波器。 量化器包括计数器，参考电压发生器和比较器。 计数器被配置为提供估计环路滤波器的输出的多位输出值。 参考电压发生器被配置为基于计数器的输出值产生参考电压斜坡。 比较器耦合到参考电压发生器，以将参考电压斜坡与环路滤波器的输出进行比较。