公开(公告)号：US20140327047A1

公开(公告)日：2014-11-06

申请号：US13886744

申请日：2013-05-03

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Asad Mahmood HAIDER ,  Jungwoo JOH

IPC: H01L21/28 ,  H01L29/66 ,  H01L29/51 ,  H01L29/778

CPC classification number: H01L29/7787 ,  H01L21/28264 ,  H01L21/28575 ,  H01L29/2003 ,  H01L29/42368 ,  H01L29/452 ,  H01L29/4975 ,  H01L29/518 ,  H01L29/66462

Abstract: A semiconductor device may be formed by forming a silicon-containing gate dielectric layer over a semiconductor layer. A gate metal layer is formed over the gate dielectric layer; the gate metal layer includes 2 atomic percent to 10 atomic percent silicon during formation. The gate metal layer is patterned to form a metal gate. Source and drain contact holes are subsequently formed, and contact metal is formed and patterned in the contact holes. A subsequent contact anneal heats the contact metal and gate for at least 30 seconds at a temperature of at least 750° C.

Abstract translation: 可以通过在半导体层上形成含硅栅极电介质层来形成半导体器件。 栅极金属层形成在栅极介质层上; 栅极金属层在形成期间包括2原子％至10原子％的硅。 栅极金属层被图案化以形成金属栅极。 随后形成源极和漏极接触孔，并在接触孔中形成接触金属并图案化。 随后的接触退火在至少750℃的温度下加热接触金属和栅极至少30秒。

公开(公告)号：US20160218202A1

公开(公告)日：2016-07-28

申请号：US15090689

申请日：2016-04-05

Applicant: Texas Instruments Incorporated

Inventor： Qhalid FAREED ,  Asad Mahmood HAIDER

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/15

CPC classification number: H01L21/02505 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/02507 ,  H01L21/02513 ,  H01L21/0254 ,  H01L29/1066 ,  H01L29/155 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/518 ,  H01L29/66462 ,  H01L29/66522 ,  H01L29/7781 ,  H01L29/7784 ,  H01L29/7787 ,  H01L29/78

Abstract: A method of fabricating a multi-layer epitaxial buffer layer stack for transistors includes depositing a buffer stack on a substrate. A first voided Group IIIA-N layer is deposited on the substrate, and a first essentially void-free Group IIIA-N layer is then deposited on the first voided Group IIIA-N layer. A first high roughness Group IIIA-N layer is deposited on the first essentially void-free Group IIIA-N layer, and a first essentially smooth Group IIIA-N layer is deposited on the first high roughness Group IIIA-N layer. At least one Group IIIA-N surface layer is then deposited on the first essentially smooth Group IIIA-N layer.

Abstract translation: 制造用于晶体管的多层外延缓冲层堆叠的方法包括在衬底上沉积缓冲层。 第一空穴IIIA-N层被沉积在衬底上，然后在第一空穴IIIA-N层上沉积第一基本无空隙的IIIA-N层。 第一高粗糙度组IIIA-N层沉积在第一基本无空隙的IIIA-N族第一层上，并且第一基本上平滑的IIIA-N层沉积在第一高粗糙度IIIA-N层上。 然后将至少一个IIIA-N族表面层沉积在第一基本上平滑的IIIA-N层上。

公开(公告)号：US20150214069A1

公开(公告)日：2015-07-30

申请号：US14684663

申请日：2015-04-13

Applicant: Texas Instruments Incorporated

Inventor： Asad Mahmood HAIDER

IPC: H01L21/324 ,  H01L21/02

CPC classification number: H01L21/324 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/02192 ,  H01L21/02194 ,  H01L21/02197 ,  H01L21/02282 ,  H01L27/20 ,  H01L41/1875 ,  H01L41/1876 ,  H01L41/318

Abstract: A process of forming an integrated circuit containing a piezoelectric thin film by forming a sol gel layer, drying in at least 1 percent relative humidity, baking starting between 100 and 225° C. increasing to between 275 and 425° C. over at least 2 minutes, and forming the piezoelectric thin film by baking the sol gel layer between 250 and 350° C. for at least 20 seconds, annealing between 650 and 750° C. for at least 60 seconds in an oxidizing ambient pressure between 700 and 1000 torr and a flow rate between 3 and 7 slm, followed by annealing between 650 and 750° C. for at least 20 seconds in a pressure between 4 and 10 torr and a flow rate of at least 5 slm, followed by ramping down the temperature.

Abstract translation: 通过形成溶胶凝胶层形成包含压电薄膜的集成电路，在至少1％相对湿度下干燥，在100和225℃之间进行烘烤，在至少2℃至275℃和425℃之间进行烘烤 分钟，并通过将溶胶凝胶层在250和350℃之间烘烤至少20秒形成压电薄膜，在700和1000托之间的氧化环境压力下在650和750℃之间退火至少60秒 流速在3和7slm之间，然后在4和10托之间的压力和至少5slm的流速下在650和750℃之间退火至少20秒，随后降低温度。

公开(公告)号：US20150187570A1

公开(公告)日：2015-07-02

申请号：US14467688

申请日：2014-08-25

Applicant: Texas Instruments Incorporated

Inventor： Asad Mahmood HAIDER ,  John Britton ROBBINS

IPC: H01L21/02

CPC classification number: H01L21/02087 ,  B05D1/005 ,  H01L21/0206 ,  H01L21/02197 ,  H01L21/02282 ,  H01L21/02334 ,  H01L21/6715 ,  H01L28/55

Abstract: Use of a non-solvent for the edge bead removal of spin-coated PZT or PLZT thinfilms, eliminates swelling of the exposed edges of the PZT or PLZT thinfilms and eliminates delamination and formation of particle defects in subsequent bake and anneal steps.

Abstract translation: 使用非溶剂去除旋涂PZT或PLZT薄膜的边缘珠，消除PZT或PLZT薄膜的暴露边缘的溶胀，并消除后续烘烤和退火步骤中的分层和颗粒缺陷的形成。

公开(公告)号：US20170133221A1

公开(公告)日：2017-05-11

申请号：US15414224

申请日：2017-01-24

Applicant: Texas Instruments Incorporated

Inventor： Qhalid FAREED ,  Asad Mahmood HAIDER

IPC: H01L21/02 ,  H01L29/778 ,  H01L29/205 ,  H01L29/66 ,  H01L29/20

CPC classification number: H01L21/02505 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/02507 ,  H01L21/02513 ,  H01L21/0254 ,  H01L29/1066 ,  H01L29/155 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/518 ,  H01L29/66462 ,  H01L29/66522 ,  H01L29/7781 ,  H01L29/7784 ,  H01L29/7787 ,  H01L29/78

Abstract: A method of fabricating a multi-layer epitaxial buffer layer stack for transistors includes depositing a buffer stack on a substrate. A first voided Group IIIA-N layer is deposited on the substrate, and a first essentially void-free Group IIIA-N layer is then deposited on the first voided Group IIIA-N layer. A first high roughness Group IIIA-N layer is deposited on the first essentially void-free Group IIIA-N layer, and a first essentially smooth Group IIIA-N layer is deposited on the first high roughness Group IIIA-N layer. At least one Group IIIA-N surface layer is then deposited on the first essentially smooth Group IIIA-N layer.

公开(公告)号：US20150060949A1

公开(公告)日：2015-03-05

申请号：US14537455

申请日：2014-11-10

Applicant: Texas Instruments Incorporated

Inventor： Asad Mahmood HAIDER ,  Jungwoo JOH

IPC: H01L29/778 ,  H01L29/45 ,  H01L29/51 ,  H01L29/20 ,  H01L29/49

CPC classification number: H01L29/7787 ,  H01L21/28264 ,  H01L21/28575 ,  H01L29/2003 ,  H01L29/42368 ,  H01L29/452 ,  H01L29/4975 ,  H01L29/518 ,  H01L29/66462

Abstract: A semiconductor device may be formed by forming a silicon-containing gate dielectric layer over a semiconductor layer. A gate metal layer is formed over the gate dielectric layer; the gate metal layer includes 2 atomic percent to 10 atomic percent silicon during formation. The gate metal layer is patterned to form a metal gate. Source and drain contact holes are subsequently formed, and contact metal is formed and patterned in the contact holes. A subsequent contact anneal heats the contact metal and gate for at least 30 seconds at a temperature of at least 750° C.

Abstract translation: 可以通过在半导体层上形成含硅栅极电介质层来形成半导体器件。 栅极金属层形成在栅极介质层上; 栅极金属层在形成期间包括2原子％至10原子％的硅。 栅极金属层被图案化以形成金属栅极。 随后形成源极和漏极接触孔，并在接触孔中形成接触金属并图案化。 随后的接触退火在至少750℃的温度下加热接触金属和栅极至少30秒。