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公开(公告)号：US12166493B2
公开(公告)日：2024-12-10
申请号：US18190501
申请日：2023-03-27
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Ryan Alexander Smith
Abstract: In an example, a system includes a phase-locked loop including a charge pump coupled to a phase frequency detector, a low-pass filter coupled to the charge pump, and a VCO coupled to the low-pass filter, where the charge pump is configured to provide a charge pump current to the low-pass filter. The system also includes a current source configured to provide a bias current to the charge pump. The system includes a first bias compensation circuit configured to increase the bias current responsive to a control voltage provided to the VCO being within a first range. The system also includes a second bias compensation circuit configured to decrease the bias current responsive to the control voltage provided to the VCO being within a second range.
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公开(公告)号：US12181913B2
公开(公告)日：2024-12-31
申请号：US17562216
申请日：2021-12-27
Applicant: TEXAS INSTRUMENTS INCORPORATED
Abstract: An electronic circuit includes an oscillator circuit, a first divider circuit, a synchronization control circuit, and a peripheral circuit. The oscillator circuit is configured to generate a base frequency clock. The first divider circuit is configured to divide the base frequency clock by a first selectable divisor to generate a divided clock. The synchronization control circuit is configured to generate a synchronization pulse that controls a change of the first selectable divisor in the first divider circuit from a first value to a second value. A pulse width of the synchronization pulse is based on the first value of the first selectable divisor. The peripheral circuit is coupled to the first divider circuit and the synchronization control circuit. The peripheral circuit includes a second divider circuit. The second divider circuit divides the divided clock by a second selectable divisor, and change the second selectable divisor responsive to the synchronization pulse.
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Patent Agency Ranking
公开(公告)号：US11811411B2
公开(公告)日：2023-11-07
申请号：US17734227
申请日：2022-05-02
Applicant: Texas Instruments Incorporated
Inventor： Abhijit Kumar Das , Ryan Alexander Smith
IPC: H03K5/1252 , H03K17/16
CPC classification number: H03K5/1252 , H03K17/16
Abstract: A glitch filter system includes an input stage to receive an input signal, a first output to provide a first digital signal, and a second output to provide a second digital signal. A C-element of such system receives the first digital signal and the second digital signal and provides a third digital signal at a first logic state in response to each of the first and second digital signals having a second logic state opposite the first logic state. An output latch of such system provides an output signal at the second logic state in response to the first logic state of the third digital. The output latch also receives the first and second digital signals to maintain the first logic state of the third digital signal in response to one of the first and second digital signals changing from the second logic state to the first logic state.
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公开(公告)号：US11863193B2
公开(公告)日：2024-01-02
申请号：US17389240
申请日：2021-07-29
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Ryan Alexander Smith
IPC: H03L7/099 , G04F10/00 , H03K3/037 , H03K19/0175 , H03M7/16
CPC classification number: H03L7/0995 , G04F10/005 , H03K3/037 , H03K19/017509 , H03M7/16 , H03L2207/50
Abstract: A system includes a ring oscillator including an odd number of inverters arranged in a ring. The system also includes a time to digital converter including an odd number of flops, where each of the flops is coupled to an output of a different inverter. The system includes a level shifter coupled to the inverters and to the flops. The system also includes a Gray counter coupled to at least one of the flops. The system includes a decoder coupled to the time to digital converter. The system also includes a phase frequency detector coupled to the decoder.
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公开(公告)号：US11323106B1
公开(公告)日：2022-05-03
申请号：US17101511
申请日：2020-11-23
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Abhijit Kumar Das , Ryan Alexander Smith
IPC: H03K5/1252 , H03K17/16
Abstract: One example includes a glitch filter system. The system includes an input stage to receive an input signal, a first output to provide a first digital signal, and a second output to provide a second digital signal. A C-element receives the first digital signal and the second digital signal and provides a third digital signal at a first logic state in response to each of the first and second digital signals having a second logic state opposite the first logic state. An output latch provides an output signal at the second logic state in response to the first logic state of the third digital. The output latch also receives the first and second digital signals to maintain the first logic state of the third digital signal in response to one of the first and second digital signals changing from the second logic state to the first logic state.
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公开(公告)号：US20230205256A1
公开(公告)日：2023-06-29
申请号：US17562216
申请日：2021-12-27
Applicant: TEXAS INSTRUMENTS INCORPORATED
CPC classification number: G06F1/12 , H03K21/023
Abstract: An electronic circuit includes an oscillator circuit, a first divider circuit, a synchronization control circuit, and a peripheral circuit. The oscillator circuit is configured to generate a base frequency clock. The first divider circuit is configured to divide the base frequency clock by a first selectable divisor to generate a divided clock. The synchronization control circuit is configured to generate a synchronization pulse that controls a change of the first selectable divisor in the first divider circuit from a first value to a second value. A pulse width of the synchronization pulse is based on the first value of the first selectable divisor. The peripheral circuit is coupled to the first divider circuit and the synchronization control circuit. The peripheral circuit includes a second divider circuit. The second divider circuit divides the divided clock by a second selectable divisor, and change the second selectable divisor responsive to the synchronization pulse.
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公开(公告)号：US20220263500A1
公开(公告)日：2022-08-18
申请号：US17734227
申请日：2022-05-02
Applicant: Texas Instruments Incorporated
Inventor： Abhijit Kumar Das , Ryan Alexander Smith
IPC: H03K5/1252 , H03K17/16
Abstract: One example includes a glitch filter system. The system includes an input stage to receive an input signal, a first output to provide a first digital signal, and a second output to provide a second digital signal. A C-element receives the first digital signal and the second digital signal and provides a third digital signal at a first logic state in response to each of the first and second digital signals having a second logic state opposite the first logic state. An output latch provides an output signal at the second logic state in response to the first logic state of the third digital. The output latch also receives the first and second digital signals to maintain the first logic state of the third digital signal in response to one of the first and second digital signals changing from the second logic state to the first logic state.
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