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    Acoustic waveguide with diffraction grating
    2.
    发明授权
    Acoustic waveguide with diffraction grating 有权

    公开(公告)号：US12191554B2

    公开(公告)日：2025-01-07

    申请号：US17347365

    申请日：2021-06-14

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Bichoy Bahr ,  Benjamin Stassen Cook ,  Scott R. Summerfelt

    IPC: H01P3/12 ,  H01L23/31 ,  H01L25/18 ,  H05K1/18

    Abstract: In some examples, a package comprises a semiconductor die having a first surface and a second surface opposing the first surface, the semiconductor die including circuitry formed in the first surface. The package includes an acoustic waveguide in the semiconductor die, the acoustic waveguide including an array of capacitors. The array of capacitors includes a transducer portion and a diffraction grating portion. The transducer portion is configured to convert signals between electrical signals and acoustic waves, and the diffraction grating portion is configured to direct the acoustic waves toward and receive the acoustic waves from the second surface.

    DILUTION DOPED INTEGRATED CIRCUIT RESISTORS
    5.
    发明申请
    DILUTION DOPED INTEGRATED CIRCUIT RESISTORS 有权
    稀释集成电路电阻器

    公开(公告)号：US20150187583A1

    公开(公告)日：2015-07-02

    申请号：US14576680

    申请日：2014-12-19

    Applicant: Texas Instruments Incorporated

    Inventor： Scott K. Montgomery ,  Scott R. Summerfelt

    IPC: H01L21/266 ,  H01L49/02 ,  H01L21/8234

    CPC classification number: H01L21/266 ,  H01L27/0629 ,  H01L28/20

    Abstract: A process for forming an integrated circuit with a dilution doped resistor with a resistance that may be tuned by partially blocking the implant used to dope the resistor. A process for forming an integrated circuit with a dilution doped polysilicon resistor by partially blocking the resistor dopant implant from a portion of the polysilicon resistor body.

    Abstract translation: 用具有电阻的稀释掺杂电阻器形成集成电路的过程可以通过部分阻挡用于掺杂电阻器的注入来调节。 通过从多晶硅电阻体的一部分部分地阻挡电阻器掺杂剂注入来形成具有稀释多晶硅电阻器的集成电路的工艺。

    Contact and Via Interconnects Using Metal Around Dielectric Pillars
    7.
    发明申请
    Contact and Via Interconnects Using Metal Around Dielectric Pillars 审中-公开
    接触和通过互连使用电介质支柱附近的金属

    公开(公告)号：US20140094028A1

    公开(公告)日：2014-04-03

    申请号：US14098255

    申请日：2013-12-05

    Applicant: Texas Instruments Incorporated

    Inventor： Scott R. Summerfelt

    IPC: H01L21/768

    CPC classification number: H01L21/76885 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/5227 ,  H01L23/5286 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/53242 ,  H01L23/53257 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An integrated circuit containing a vertical interconnect that includes a region of interconnect metal continuously surrounding one or more dielectric pillars. The vertical interconnect electrically contacts a top surface of a lower conductive structure. An upper conductive structure contacts a top surface of the vertical interconnect. A process of forming an integrated circuit that includes forming a vertical interconnect that has a region of interconnect metal continuously surrounding one or more dielectric pillars. The vertical interconnect electrically contacts a top surface of a lower conductive structure, and an upper conductive structure contacts a top surface of the vertical interconnect.

    Abstract translation: 一种包含垂直互连的集成电路，其包括连续围绕一个或多个介电柱的互连金属区域。 垂直互连电接触下导电结构的顶表面。 上导电结构接触垂直互连的顶表面。 形成集成电路的过程包括形成具有连续围绕一个或多个介电柱的互连金属区域的垂直互连。 垂直互连电接触下导电结构的顶表面，并且上导电结构接触垂直互连的顶表面。

    DIFFERENTIAL PLATE LINE SCREEN TEST FOR FERROELECTRIC LATCH CIRCUITS
    8.
    发明申请
    DIFFERENTIAL PLATE LINE SCREEN TEST FOR FERROELECTRIC LATCH CIRCUITS 有权
    用于电磁绞线电路的差分线路屏蔽测试

    公开(公告)号：US20130021833A1

    公开(公告)日：2013-01-24

    申请号：US13626531

    申请日：2012-09-25

    Applicant: Texas Instruments Incorporated

    Inventor： Scott R. Summerfelt ,  John Anthony Rodriguez ,  Hugh P. McAdams ,  Steven Craig Bartling

    IPC: G11C11/22

    CPC classification number: G11C29/50 ,  G11C11/22

    Abstract: Non-volatile latch circuits, such as in memory cells and flip-flops, that are constructed for reliability screening. The non-volatile latch circuits each include ferroelectric capacitors coupled to storage nodes, for example at the outputs of cross-coupled inverters. Separate plate lines are connected to the ferroelectric capacitors of the complementary storage nodes. A time-zero test of the latch stability margin is performed by setting a logic state at the storage nodes, then programming the state into the ferroelectric capacitors by polarization. After power-down, the plate lines are biased with a differential voltage relative to one another, and the latch is then powered up to attempt recall of the programmed state. The differential voltage disturbs the recall, and provides a measure of the cell margin and its later-life reliability.

    Abstract translation: 构建用于可靠性筛选的非易失性锁存电路，例如在存储器单元和触发器中。 非易失性锁存电路各自包括耦合到存储节点的铁电电容器，例如在交叉耦合的反相器的输出端。 单独的板线连接到互补存储节点的铁电电容器。 通过在存储节点设置逻辑状态，然后通过极化将状态编程到铁电电容器中来执行锁存稳定裕度的时间零测试。 掉电后，电路板以相对于彼此的差分电压偏置，然后锁存器上电以尝试调用编程状态。 差分电压会干扰召回，并提供信号余量的测量及其后期寿命的可靠性。

    Differential plate line screen test for ferroelectric latch circuits
    10.
    发明授权
    Differential plate line screen test for ferroelectric latch circuits 有权

    公开(公告)号：US08472236B2

    公开(公告)日：2013-06-25

    申请号：US13626531

    申请日：2012-09-25

    Applicant: Texas Instruments Incorporated

    Inventor： Scott R. Summerfelt ,  John Anthony Rodriguez ,  Hugh P. McAdams ,  Steven Craig Bartling

    IPC: G11C11/22

    CPC classification number: G11C29/50 ,  G11C11/22

    Abstract: Non-volatile latch circuits, such as in memory cells and flip-flops, that are constructed for reliability screening. The non-volatile latch circuits each include ferroelectric capacitors coupled to storage nodes, for example at the outputs of cross-coupled inverters. Separate plate lines are connected to the ferroelectric capacitors of the complementary storage nodes. A time-zero test of the latch stability margin is performed by setting a logic state at the storage nodes, then programming the state into the ferroelectric capacitors by polarization. After power-down, the plate lines are biased with a differential voltage relative to one another, and the latch is then powered up to attempt recall of the programmed state. The differential voltage disturbs the recall, and provides a measure of the cell margin and its later-life reliability.

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