公开(公告)号：US20190252397A1

公开(公告)日：2019-08-15

申请号：US16333096

申请日：2016-09-21

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Wataru SAKAMOTO ,  Hiroshi NAKAKI ,  Hanae ISHIHARA

IPC: H01L27/11568 ,  H01L27/11578 ,  H01L27/11573 ,  H01L29/792

CPC classification number: H01L27/11568 ,  H01L27/11573 ,  H01L27/11578 ,  H01L29/788 ,  H01L29/792

Abstract: A semiconductor device of the embodiment includes a stacked body, a first insulating layer, first and second staircase portions 2, and a second insulating layer 46. The stacked body includes a first electrode layer 41 (WLDD) and a second electrode layer 41 (SGD). The first and second staircase portions 2 are provided in a first end portion 101 a second end region 102. The second insulating layer 46 extends in the X-direction. The second insulating layer divides the second electrode layer 41 (SGD) in the X-direction direction. A length L1 in the X-direction of the second insulating layer 46 is longer than a length L2 in the x-direction of the second electrode layer 41 (SGD) and shorter than a length L3 in the X-direction of the first electrode layer 41 (WLDD).

公开(公告)号：US20190296117A1

公开(公告)日：2019-09-26

申请号：US16130432

申请日：2018-09-13

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Megumi ISHIDUKI ,  Hiroshi NAKAKI ,  Takamasa ITO

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/792 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/11575

Abstract: A semiconductor device includes a base body, a stacked body on the base body and a first columnar part. The base body includes a substrate, a first insulating film on the substrate, a first conductive film on the first insulating film, and a first semiconductor part on the first conductive film. The stacked body includes conductive layers and insulating layers stacked alternately in a stacking direction. The first columnar part is provided inside the stacked body and the first semiconductor part. The first columnar part includes a semiconductor body and a memory film between the semiconductor body and conductive layers. The semiconductor body extends in the stacking direction. The first columnar part has a first diameter and a second diameter in a first direction crossing the stacking direction. The first diameter inside the first semiconductor part is larger than the second diameter inside the stacked body.

公开(公告)号：US20190287998A1

公开(公告)日：2019-09-19

申请号：US16127763

申请日：2018-09-11

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Hisashi HARADA ,  Jun NISHIMURA ,  Ayaha HACHISUGA ,  Hiroshi NAKAKI ,  Yukie MIYAZAKI ,  Keisuke SUDA ,  Yu HIROTSU

IPC: H01L27/11582 ,  H01L29/10 ,  H01L29/06 ,  H01L27/11565 ,  H01L23/528

Abstract: A semiconductor device includes a base body portion, a stacked body, a pedestal portion, a plate portion, and first and second columnar portions. The base body portion includes a doped semiconductor film and a semiconductor portion. The doped semiconductor film includes first and second portions. The semiconductor portion includes a first region overlapping the first portion, and a second region overlapping the second portion and being a body different from the first region. The pedestal portion is provided in the second region. The plate portion contacts the pedestal portion and the first region. The first columnar portion includes a semiconductor layer. The semiconductor layer is adjacent to the plate portion with the stacked body interposed, and contacts the first region. The second columnar portion is adjacent to the plate portion with the stacked body interposed, and is adjacent to the pedestal portion with the second region interposed.

公开(公告)号：US20190172836A1

公开(公告)日：2019-06-06

申请号：US16109370

申请日：2018-08-22

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Shigeki KOBAYASHI ,  Hiroshi NAKAKI

IPC: H01L27/11573 ,  H01L27/11582 ,  H01L21/768

Abstract: A storage device includes a conductive layer, a plurality of electrode layers stacked on the conductive layer, a wiring above the plurality of electrode layers, an interlayer insulating film between the plurality of electrode layers and the wiring, a semiconductor film penetrating the plurality of electrode layers and the interlayer insulating film in a stacking direction of the plurality of electrode layers, a contact plug penetrating the interlayer insulating film in the stacking direction, and connected to each of the plurality of electrode layers, and a conductive film in the vicinity of the contact plug and penetrating at least one of the plurality of electrode layers in the stacking direction. The semiconductor film is electrically connected to the conductive layer and the wiring, and an entire upper end of the conductive film is covered by an insulating layer.

公开(公告)号：US20190296042A1

公开(公告)日：2019-09-26

申请号：US16127500

申请日：2018-09-11

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Hiroshi NAKAKI ,  Kotaro FUJII

IPC: H01L27/11582 ,  H01L29/66

Abstract: A method for manufacturing a semiconductor memory device includes forming a plurality of connection portions on a plurality of main body portions by filling a semiconductor material into a plurality of second through-holes, and after the forming of the plurality of connection portions, removing the third layer and a remaining portion of the second layer, the remaining portion of the second layer not being removed in the removing of the portion of the second layer.

公开(公告)号：US20190081064A1

公开(公告)日：2019-03-14

申请号：US15909494

申请日：2018-03-01

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Hiroshi NAKAKI ,  Yosuke MITSUNO ,  Tatsuya OKAMOTO

IPC: H01L27/11582 ,  H01L29/10 ,  H01L29/51 ,  H01L29/04 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G11C16/14

Abstract: A semiconductor memory device includes a first semiconductor well of a first conductivity type in a memory cell region and a contact region of a substrate, a second semiconductor well of a second conductivity type in the first semiconductor well in the contact region, a plurality of electrode films stacked on the first semiconductor well and spaced from one another in a first direction, the plurality of electrode films extending in a second direction within the memory cell region into the contact region, a first semiconductor pillar extending in the second direction through the plurality of electrode films in the memory cell region, a second semiconductor pillar extending in the second direction through at least one electrode film in the contact region, a charge storage film between the first semiconductor pillar and each electrode film, an insulating film between the second semiconductor pillar and the at least one electrode film.

公开(公告)号：US20210358900A1

公开(公告)日：2021-11-18

申请号：US17389445

申请日：2021-07-30

Applicant: Toshiba Memory Corporation

Inventor： Hiroshi NAKAKI

IPC: H01L25/18 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L27/11582

Abstract: In one embodiment, a semiconductor device includes a first substrate, and a plurality of electrode layers provided above the first substrate and stacked in a first direction. The device further includes a first semiconductor layer extending in the first direction in the plurality of electrode layers, and a metal layer provided above an uppermost one of the plurality of electrode layers and extending to cross the first direction. The device further includes a second semiconductor layer including an impurity diffusion layer that is provided between the first semiconductor layer and the metal layer, electrically connects the first semiconductor layer with the metal layer, and has an impurity concentration higher than an impurity concentration of the first semiconductor layer.

公开(公告)号：US20200286876A1

公开(公告)日：2020-09-10

申请号：US16541370

申请日：2019-08-15

Applicant: Toshiba Memory Corporation

Inventor： Hiroshi NAKAKI

IPC: H01L25/18 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00

Abstract: In one embodiment, a semiconductor device includes a first substrate, and a plurality of electrode layers provided above the first substrate and stacked in a first direction. The device further includes a first semiconductor layer extending in the first direction in the plurality of electrode layers, and a metal layer provided above an uppermost one of the plurality of electrode layers and extending to cross the first direction. The device further includes a second semiconductor layer including an impurity diffusion layer that is provided between the first semiconductor layer and the metal layer, electrically connects the first semiconductor layer with the metal layer, and has an impurity concentration higher than an impurity concentration of the first semiconductor layer.