公开(公告)号：US20190326310A1

公开(公告)日：2019-10-24

申请号：US16291347

申请日：2019-03-04

Applicant: Toshiba Memory Corporation

Inventor： Yoshiaki FUKUZUMI ,  Keisuke SUDA ,  Fumiki AISO ,  Atsushi FUKUMOTO

IPC: H01L27/11556 ,  H01L27/11582 ,  G11C5/06 ,  G11C16/04

Abstract: A semiconductor memory includes a substrate, a source line layer above the substrate in a memory region and a peripheral region of the substrate, a first insulating layer above the source line layer, a first conductive layer on the first insulating layer in the memory and peripheral regions, an alternating stack of a plurality of second insulating layers and a plurality of second conductive layers on the first conductive layer in the memory region, and a plurality of pillars extending through the alternating stack of the second insulating layers and the second conductive layers, the first conductive layer, and the first insulating layer in the memory region. A bottom end of each of the pillars is in the source line layer in a thickness direction. A carrier density of the source line layer is higher in the memory region than in the peripheral region.

公开(公告)号：US20220077170A1

公开(公告)日：2022-03-10

申请号：US17524984

申请日：2021-11-12

Applicant: Toshiba Memory Corporation

Inventor： Yoshiaki FUKUZUMI ,  Keisuke SUDA ,  Fumiki AISO ,  Atsushi FUKUMOTO

IPC: H01L27/11556 ,  H01L27/11582 ,  G11C16/04 ,  G11C5/06

Abstract: A semiconductor memory includes a substrate, a source line layer above the substrate in a memory region and a peripheral region of the substrate, a first insulating layer above the source line layer, a first conductive layer on the first insulating layer in the memory and peripheral regions, an alternating stack of a plurality of second insulating layers and a plurality of second conductive layers on the first conductive layer in the memory region, and a plurality of pillars extending through the alternating stack of the second insulating layers and the second conductive layers, the first conductive layer, and the first insulating layer in the memory region. A bottom end of each of the pillars is in the source line layer in a thickness direction. A carrier density of the source line layer is higher in the memory region than in the peripheral region.

公开(公告)号：US20190287998A1

公开(公告)日：2019-09-19

申请号：US16127763

申请日：2018-09-11

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Hisashi HARADA ,  Jun NISHIMURA ,  Ayaha HACHISUGA ,  Hiroshi NAKAKI ,  Yukie MIYAZAKI ,  Keisuke SUDA ,  Yu HIROTSU

IPC: H01L27/11582 ,  H01L29/10 ,  H01L29/06 ,  H01L27/11565 ,  H01L23/528

Abstract: A semiconductor device includes a base body portion, a stacked body, a pedestal portion, a plate portion, and first and second columnar portions. The base body portion includes a doped semiconductor film and a semiconductor portion. The doped semiconductor film includes first and second portions. The semiconductor portion includes a first region overlapping the first portion, and a second region overlapping the second portion and being a body different from the first region. The pedestal portion is provided in the second region. The plate portion contacts the pedestal portion and the first region. The first columnar portion includes a semiconductor layer. The semiconductor layer is adjacent to the plate portion with the stacked body interposed, and contacts the first region. The second columnar portion is adjacent to the plate portion with the stacked body interposed, and is adjacent to the pedestal portion with the second region interposed.

公开(公告)号：US20220115403A1

公开(公告)日：2022-04-14

申请号：US17559786

申请日：2021-12-22

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Takayuki MARUYAMA ,  Yoshiaki FUKUZUMI ,  Yuki SUGIURA ,  Shinya ARAI ,  Fumie KIKUSHIMA ,  Keisuke SUDA ,  Takashi ISHIDA

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L21/768

Abstract: A semiconductor memory device includes a plurality of electrode layers stacked above a first semiconductor layer, a second semiconductor layer and a first film. The second semiconductor layer extends through the plurality of electrode layers in a stacking direction of the plurality of electrode layers. The second semiconductor layer includes an end portion inside the first semiconductor layer. The first film is positioned inside the first semiconductor layer and contacts the first semiconductor layer. The first semiconductor layer includes a first portion, a second portion, and a third portion. The first film is positioned between the first portion and the second portion. The third portion links the first portion and the second portion. The third portion is positioned between the first film and the second semiconductor layer. The second semiconductor layer includes a contact portion contacting the third portion of the first semiconductor layer.