公开(公告)号：US10910391B2

公开(公告)日：2021-02-02

申请号：US16552255

申请日：2019-08-27

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Takayuki Hashimoto ,  Ayaha Hachisuga ,  Jun Nishimura

IPC: H01L27/11556 ,  H01L27/11524

Abstract: A semiconductor memory device comprises a substrate, first semiconductor films extending in a first direction crossing a surface of the substrate and arranged in a second direction and in a third direction, a conductive layer which covers peripheral faces of the first semiconductor films on a cross-section crossing the first direction, and a contact which extends in the first direction. Here, when straight lines disposed at equal intervals in the second direction on the cross-section and perpendicular to the second direction are defined as first to third straight lines, a first number of the first semiconductor films are provided on the first straight line, a second number less than the first number of the first semiconductor films are provided on the second straight line, a third number less than the second number of the first semiconductor films are provided on the third straight line.

公开(公告)号：US10930665B2

公开(公告)日：2021-02-23

申请号：US16536552

申请日：2019-08-09

Applicant: Toshiba Memory Corporation

Inventor： Kosuke Horibe ,  Kei Watanabe ,  Toshiyuki Sasaki ,  Tomo Hasegawa ,  Soichi Yamazaki ,  Keisuke Kikutani ,  Jun Nishimura ,  Hisashi Harada ,  Hideyuki Kinoshita

IPC: H01L27/11578 ,  G11C16/04 ,  H01L27/11565 ,  H01L27/11573

Abstract: A semiconductor device of an embodiment includes a control circuit arranged on a substrate, a first conductive layer arranged on the control circuit and containing a first element as a main component, a multilayer structure arranged on the first conductive layer and configured such that multiple second conductive layers and multiple insulating layers are alternately stacked on each other, a memory layer penetrating the multilayer structure and reaching the first conductive layer at a bottom portion, a first layer arranged between the control circuit and the first conductive layer and containing the first element as a main component, and a second layer arranged between the control circuit and the first layer and containing, as a main component, a second element different from the first element.

公开(公告)号：US20200295016A1

公开(公告)日：2020-09-17

申请号：US16564434

申请日：2019-09-09

Applicant: Toshiba Memory Corporation

Inventor： Hisashi HARADA ,  Ayaha Hachisuga ,  Jun Nishimura

IPC: H01L27/1157 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11519 ,  H01L21/28 ,  H01L27/11582 ,  H01L27/11565 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768

Abstract: A semiconductor memory device according to an embodiment includes first to third conductive layers, first and second pillars, first and second contacts, and first to third members. The first pillar penetrates the first and second conductive layers in a first area. A second pillar penetrates the first and third conductive layers in the first area. The first and second contacts are provided on the second and third conductive layers respectively in a second area. The first and second members are provided between the second and third conductive layers in the first and second area, respectively. The third member penetrates the first conductive layers. The third member is in contact with each of the second and third conductive layers, and the first and second members.

公开(公告)号：US20200075624A1

公开(公告)日：2020-03-05

申请号：US16291497

申请日：2019-03-04

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Shunsuke KASASHIMA ,  Jun Nishimura ,  Takamitsu Ochi ,  Hisashi Harada ,  Ayaha Hachisuga ,  Ayako Kawanishi

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/10

Abstract: A semiconductor memory device according to an embodiment includes: a substrate; a plurality of first gate electrodes; a first semiconductor film facing the plurality of first gate electrodes; and a first gate insulating film provided between the plurality of first gate electrodes and the first semiconductor film. Moreover, this semiconductor memory device includes: a plurality of second gate electrodes; a second semiconductor film facing the plurality of second gate electrodes; and a second gate insulating film provided between the plurality of second gate electrodes and the second semiconductor film. Moreover, this semiconductor memory device includes: a third gate electrode that is provided between the plurality of first gate electrodes and the plurality of second gate electrodes, and extends in a second direction; and a third gate insulating film provided between the third gate electrode and the first semiconductor film. Moreover, a thickness in a first direction of the third gate insulating film is larger than a width in the second direction of the first gate insulating film and the second gate insulating film.

公开(公告)号：US20200235117A1

公开(公告)日：2020-07-23

申请号：US16536552

申请日：2019-08-09

Applicant: Toshiba Memory Corporation

Inventor： Kosuke HORIBE ,  Kei Watanabe ,  Toshiyuki Sasaki ,  Tomo Hasegawa ,  Soichi Yamazaki ,  Keisuke Kikutani ,  Jun Nishimura ,  Hisashi Harada ,  Hideyuki Kinoshita

IPC: H01L27/11578 ,  H01L27/11573 ,  H01L27/11565 ,  G11C16/04

Abstract: A semiconductor device of an embodiment includes a control circuit arranged on a substrate, a first conductive layer arranged on the control circuit and containing a first element as a main component, a multilayer structure arranged on the first conductive layer and configured such that multiple second conductive layers and multiple insulating layers are alternately stacked on each other, a memory layer penetrating the multilayer structure and reaching the first conductive layer at a bottom portion, a first layer arranged between the control circuit and the first conductive layer and containing the first element as a main component, and a second layer arranged between the control circuit and the first layer and containing, as a main component, a second element different from the first element.

公开(公告)号：US10692886B2

公开(公告)日：2020-06-23

申请号：US16291497

申请日：2019-03-04

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Shunsuke Kasashima ,  Jun Nishimura ,  Takamitsu Ochi ,  Hisashi Harada ,  Ayaha Hachisuga ,  Ayako Kawanishi

IPC: H01L27/11582 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11565 ,  H01L29/10 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/28

Abstract: A semiconductor memory device according to an embodiment includes: a substrate; a plurality of first gate electrodes; a first semiconductor film facing the plurality of first gate electrodes; and a first gate insulating film provided between the plurality of first gate electrodes and the first semiconductor film. Moreover, this semiconductor memory device includes: a plurality of second gate electrodes; a second semiconductor film facing the plurality of second gate electrodes; and a second gate insulating film provided between the plurality of second gate electrodes and the second semiconductor film. Moreover, this semiconductor memory device includes: a third gate electrode that is provided between the plurality of first gate electrodes and the plurality of second gate electrodes, and extends in a second direction; and a third gate insulating film provided between the third gate electrode and the first semiconductor film. Moreover, a thickness in a first direction of the third gate insulating film is larger than a width in the second direction of the first gate insulating film and the second gate insulating film.

公开(公告)号：US10483277B2

公开(公告)日：2019-11-19

申请号：US15463169

申请日：2017-03-20

Applicant: Toshiba Memory Corporation

Inventor： Jun Nishimura

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L23/528 ,  H01L27/1157

Abstract: According to one embodiment, a semiconductor memory device includes a substrate, interconnect portions, a conductive layer, a stacked body, and columnar portions. At least one portion of the interconnect portions is provided inside the substrate, each of the interconnect portions extends in a first direction along a surface of the substrate, and the interconnect portions are arranged along a second direction crossing the first direction. The conductive layer is provided on the interconnect portions. The stacked body is provided on the conductive layer and includes electrode layers stacked to be separated from each other, and each of the electrode layers extends in the second direction. The columnar portions are provided inside the stacked body, each of the columnar portions includes a semiconductor portion extending in a stacking direction of the electrode layers and a charge storage film provided between the semiconductor portion and the stacked body.

公开(公告)号：US20180076293A1

公开(公告)日：2018-03-15

申请号：US15463137

申请日：2017-03-20

Applicant: Toshiba Memory Corporation

Inventor： Jun Nishimura

IPC: H01L29/40 ,  H01L27/1157 ,  H01L27/11582

CPC classification number: H01L29/408 ,  H01L27/11565 ,  H01L27/11582

Abstract: According to one embodiment, a semiconductor memory device includes a substrate, a stacked body, a semiconductor portion, and an insulating portion. The insulating portion is provided in the stacked body and extends in a stacking direction and a first direction along a surface of the substrate, the first direction crossing the stacking direction. The insulating portion includes a first insulating film containing silicon oxide, a second insulating film containing silicon oxide, and a third insulating film located between the first insulating film and the second insulating film and containing silicon nitride.

公开(公告)号：US20200075616A1

公开(公告)日：2020-03-05

申请号：US16552255

申请日：2019-08-27

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Takayuki Hashimoto ,  Ayaha Hachisuga ,  Jun Nishimura

IPC: H01L27/11556 ,  H01L27/11524

Abstract: A semiconductor memory device comprises a substrate, first semiconductor films extending in a first direction crossing a surface of the substrate and arranged in a second direction and in a third direction, a conductive layer which covers peripheral faces of the first semiconductor films on a cross-section crossing the first direction, and a contact which extends in the first direction. Here, when straight lines disposed at equal intervals in the second direction on the cross-section and perpendicular to the second direction are defined as first to third straight lines, a first number of the first semiconductor films are provided on the first straight line, a second number less than the first number of the first semiconductor films are provided on the second straight line, a third number less than the second number of the first semiconductor films are provided on the third straight line.

公开(公告)号：US10510770B2

公开(公告)日：2019-12-17

申请号：US16127763

申请日：2018-09-11

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Hisashi Harada ,  Jun Nishimura ,  Ayaha Hachisuga ,  Hiroshi Nakaki ,  Yukie Miyazaki ,  Keisuke Suda ,  Yu Hirotsu

IPC: H01L27/11582 ,  H01L29/06 ,  H01L27/11565 ,  H01L23/528 ,  H01L29/10 ,  H01L21/28 ,  H01L27/11551 ,  H01L27/11578 ,  H01L23/522 ,  H01L27/24 ,  H01L27/06 ,  H01L21/822 ,  H01L21/02 ,  H01L29/66 ,  H01L29/51 ,  H01L21/311 ,  H01L21/027

Abstract: A semiconductor device includes a base body portion, a stacked body, a pedestal portion, a plate portion, and first and second columnar portions. The base body portion includes a doped semiconductor film and a semiconductor portion. The doped semiconductor film includes first and second portions. The semiconductor portion includes a first region overlapping the first portion, and a second region overlapping the second portion and being a body different from the first region. The pedestal portion is provided in the second region. The plate portion contacts the pedestal portion and the first region. The first columnar portion includes a semiconductor layer. The semiconductor layer is adjacent to the plate portion with the stacked body interposed, and contacts the first region. The second columnar portion is adjacent to the plate portion with the stacked body interposed, and is adjacent to the pedestal portion with the second region interposed.