公开(公告)号：US10510764B2

公开(公告)日：2019-12-17

申请号：US15948057

申请日：2018-04-09

Applicant: Toshiba Memory Corporation

Inventor： Masayoshi Tagami ,  Ryota Katsumata ,  Toru Matsuda ,  Yu Hirotsu ,  Naoki Yamamoto

IPC: H01L27/115 ,  H01L21/288 ,  H01L21/768 ,  H01L23/528 ,  H01L29/792 ,  H01L23/498 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/1157

Abstract: According to one embodiment, a semiconductor device includes a stacked body, first, second, third, and fourth insulating bodies, first and second columnar portions. The stacked body includes a conductive layer and an insulating layer stacked alternately. The first, second, third and fourth insulating bodies, the first and second columnar portions are provided inside the stacked body. The second insulating body is at a position different from the first insulating body. The third insulating body is between the first and second insulating bodies. The fourth insulating body is between the first and second insulating bodies, and includes portions contacting the third insulating body and being separated from each other with the third insulating body interposed. The first columnar portion is between the first and fourth insulating bodies. The second columnar portion is between the second and fourth insulating bodies. The first and second columnar portions include a semiconductor layer.

公开(公告)号：US11177185B2

公开(公告)日：2021-11-16

申请号：US16270635

申请日：2019-02-08

Applicant: Toshiba Memory Corporation

Inventor： Naoki Yamamoto ,  Yu Hirotsu

IPC: H01L27/11582 ,  H01L23/522 ,  H01L23/528 ,  H01L29/10 ,  H01L27/11568 ,  H01L21/66 ,  H01L21/768 ,  H01L27/11565 ,  H01L27/11575

Abstract: A semiconductor memory according to an embodiment includes first and second areas, an active region, a non-active region, a first stacked body, a plurality of first pillars, a first contact, a second stacked body, and a second contact. The active region includes part of each of the first and second areas. The non-active region includes part of each of the first and second areas. The second stacked body is in the non-active region. The second stacked body includes second insulators and second conductors which are alternately stacked. A second contact is in contact with a second conductor in a first interconnect layer and a second conductor in a second interconnect layer.

公开(公告)号：US10510770B2

公开(公告)日：2019-12-17

申请号：US16127763

申请日：2018-09-11

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Hisashi Harada ,  Jun Nishimura ,  Ayaha Hachisuga ,  Hiroshi Nakaki ,  Yukie Miyazaki ,  Keisuke Suda ,  Yu Hirotsu

IPC: H01L27/11582 ,  H01L29/06 ,  H01L27/11565 ,  H01L23/528 ,  H01L29/10 ,  H01L21/28 ,  H01L27/11551 ,  H01L27/11578 ,  H01L23/522 ,  H01L27/24 ,  H01L27/06 ,  H01L21/822 ,  H01L21/02 ,  H01L29/66 ,  H01L29/51 ,  H01L21/311 ,  H01L21/027

Abstract: A semiconductor device includes a base body portion, a stacked body, a pedestal portion, a plate portion, and first and second columnar portions. The base body portion includes a doped semiconductor film and a semiconductor portion. The doped semiconductor film includes first and second portions. The semiconductor portion includes a first region overlapping the first portion, and a second region overlapping the second portion and being a body different from the first region. The pedestal portion is provided in the second region. The plate portion contacts the pedestal portion and the first region. The first columnar portion includes a semiconductor layer. The semiconductor layer is adjacent to the plate portion with the stacked body interposed, and contacts the first region. The second columnar portion is adjacent to the plate portion with the stacked body interposed, and is adjacent to the pedestal portion with the second region interposed.

公开(公告)号：US11101279B2

公开(公告)日：2021-08-24

申请号：US16554861

申请日：2019-08-29

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Ken Komiya ,  Takamasa Ito ,  Naoki Yamamoto ,  Yu Hirotsu ,  Kazuhiro Tomishige ,  Yoshinori Nakakubo

IPC: H01L27/11556 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11582 ,  H01L23/532 ,  H01L21/02 ,  H01L21/311

Abstract: A semiconductor memory device includes: a substrate including a first and a second regions; first wiring layers disposed in a first direction; a second wiring layer; a third wiring layer closer to the substrate than the first and the second wiring layers; a semiconductor film that penetrates the first and the second wiring layers, and is connected to the third wiring layer; and a gate insulating film disposed between the semiconductor film and the first wiring layers. The first wiring layers include first conductive films opposed to the semiconductor film in the first region, and first films in the second region. The second wiring layer includes a second conductive film opposed to the semiconductor film in the first region, and a second film in the second region. The second film is different from the first films.

公开(公告)号：US20190096899A1

公开(公告)日：2019-03-28

申请号：US15948057

申请日：2018-04-09

Applicant: Toshiba Memory Corporation

Inventor： Masayoshi Tagami ,  Ryota Katsumata ,  Toru Matsuda ,  Yu Hirotsu ,  Naoki Yamamoto

IPC: H01L27/11524 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11556

CPC classification number: H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582

Abstract: According to one embodiment, a semiconductor device includes a stacked body, first, second, third, and fourth insulating bodies, first and second columnar portions. The stacked body includes a conductive layer and an insulating layer stacked alternately. The first, second, third and fourth insulating bodies, the first and second columnar portions are provided inside the stacked body. The second insulating body is at a position different from the first insulating body. The third insulating body is between the first and second insulating bodies. The fourth insulating body is between the first and second insulating bodies, and includes portions contacting the third insulating body and being separated from each other with the third insulating body interposed. The first columnar portion is between the first and fourth insulating bodies. The second columnar portion is between the second and fourth insulating bodies. The first and second columnar portions include a semiconductor layer.