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公开(公告)号：US10672468B2
公开(公告)日：2020-06-02
申请号：US16353292
申请日：2019-03-14
发明人： Ryu Ogiwara , Daisaburo Takashima
IPC分类号： G11C13/00
摘要： According to one embodiment, a memory device includes a first circuit including a resistance change memory element capable of setting a low resistance state or a high resistance state according to a falling speed of an applied voltage, and a first rectifier element connected in series to the resistance change memory element, and a second circuit including a current source, and a second rectifier element connected in series to the current source, the second circuit having a mirror relationship with the first circuit.
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公开(公告)号：US09928903B2
公开(公告)日：2018-03-27
申请号：US15248216
申请日：2016-08-26
发明人： Ryu Ogiwara , Daisaburo Takashima
CPC分类号： G11C13/0004 , G11C7/04 , G11C11/1655 , G11C11/1675 , G11C11/1697 , G11C13/0026 , G11C13/0038 , G11C13/004 , G11C13/0069 , G11C2013/0054 , G11C2013/009 , G11C2213/72
摘要： According to one embodiment, a semiconductor storage device includes: a memory cell including a variable resistance element; a bit line coupled to the memory cell; and a first circuit applying a first voltage to the bit line in a write operation for the memory cell. When a temperature of the variable resistance element is lower than or equal to a first temperature, a temperature coefficient of the first voltage is 0. When the temperature of the variable resistance element is higher than the first temperature, the temperature coefficient of the first voltage is negative.
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公开(公告)号：US10923189B2
公开(公告)日：2021-02-16
申请号：US16353172
申请日：2019-03-14
摘要： According to one embodiment, a memory device includes a memory cell including a resistance change memory element and a selector element, a word line, a bit line connected to one end of the memory cell, an operational amplifier including a non-inverting input connected to the bit line, an output circuit including a first terminal connected to an output of the operational amplifier, a second terminal connected to the bit line, and a charge/discharge circuit including a capacitor, a charge circuit and a discharge circuit, each including one end connected to an inverting input of the operational amplifier. At the time of falling of a write voltage for the memory cell, a potential of the other end of the memory cell is set higher than a potential of the other end of the discharge circuit.
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公开(公告)号：US10803932B1
公开(公告)日：2020-10-13
申请号：US16559370
申请日：2019-09-03
摘要： According to one embodiment, a storage device includes: a memory cell including a storage component to which a plurality of data values are allowed to set in response to a plurality of resistance values of the storage component and a selector connected in series to the storage component; a word line configured to provide a signal to select the memory cell; a bit line configured to receive a data signal from the memory cell; a first conversion circuit configured to nonlinearly convert a first current, generated in response to the data signal input to the bit line, into a first voltage; and a comparison circuit configured to compare the first voltage, converted by the first conversion circuit, with a plurality of reference voltages.
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公开(公告)号：US20200098426A1
公开(公告)日：2020-03-26
申请号：US16353172
申请日：2019-03-14
摘要： According to one embodiment, a memory device includes a memory cell including a resistance change memory element and a selector element, a word line, a bit line connected to one end of the memory cell, an operational amplifier including a non-inverting input connected to the bit line, an output circuit including a first terminal connected to an output of the operational amplifier, a second terminal connected to the bit line, and a charge/discharge circuit including a capacitor, a charge circuit and a discharge circuit, each including one end connected to an inverting input of the operational amplifier. At the time of falling of a write voltage for the memory cell, a potential of the other end of the memory cell is set higher than a potential of the other end of the discharge circuit.
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公开(公告)号：US10410720B2
公开(公告)日：2019-09-10
申请号：US15694957
申请日：2017-09-04
IPC分类号： G11C13/00 , H01L23/528 , H01L45/00 , H01L27/24 , G11C7/04
摘要： A semiconductor memory device includes a first conductor extending in a first direction and a second conductor extending in a second direction and disposed above the first conductor in a third direction. Third and fourth conductors extend in the first direction and adjacent to each other in the second direction. The third and fourth conductors are above the second conductor. A fifth conductor includes a variable resistance unit and is between the first and second conductors. A sixth conductor includes a variable resistance unit and is between the third and second conductors. A seventh conductor includes a variable resistance unit and is between the fourth and second conductors. A center point of the fifth conductor along a width of the fifth conductor is does not fully overlap with either of the sixth or seventh conductors along the third direction.
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公开(公告)号：US09966136B2
公开(公告)日：2018-05-08
申请号：US15443084
申请日：2017-02-27
发明人： Ryu Ogiwara , Daisaburo Takashima
CPC分类号： G11C13/004 , G11C13/0004 , G11C13/0023 , G11C13/003 , G11C13/0061 , G11C13/0069 , G11C13/0097 , G11C2013/0054 , G11C2013/0092 , G11C2213/71 , G11C2213/72 , G11C2213/74 , G11C2213/75 , G11C2213/79 , H01L27/2436 , H01L45/12
摘要： According to one embodiment, a variable resistance memory includes first to third insulating layers, first and second variable resistance layers, first and second semiconductor layers, and first and second electric conductors. The first insulating layer extends in a first direction. The first and second electric conductors are in contact with the second and third insulating layers respectively. The first to third insulating layers, the first and second variable resistance layers and the first and second semiconductor layers are disposed between the first and second electric conductors in a second direction different from the first direction.
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公开(公告)号：US10950278B2
公开(公告)日：2021-03-16
申请号：US16570507
申请日：2019-09-13
摘要： According to one embodiment, a nonvolatile memory device includes first and second word lines, first and second bit lines, memory cells each including a resistance change memory element, a global word line including a first global word line portion including a first end portion, a global bit line including a first global bit line portion including a second end portion. The first and second word lines and the first global bit line portion have a first line width and a first line thickness, the first and second bit lines and the first global word line portion have a second line width and a second line thickness.
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公开(公告)号：US20190295637A1
公开(公告)日：2019-09-26
申请号：US16353292
申请日：2019-03-14
发明人： Ryu Ogiwara , Daisaburo Takashima
IPC分类号： G11C13/00
摘要： According to one embodiment, a memory device includes a first circuit including a resistance change memory element capable of setting a low resistance state or a high resistance state according to a falling speed of an applied voltage, and a first rectifier element connected in series to the resistance change memory element, and a second circuit including a current source, and a second rectifier element connected in series to the current source, the second circuit having a mirror relationship with the first circuit.
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公开(公告)号：US10032509B2
公开(公告)日：2018-07-24
申请号：US15065341
申请日：2016-03-09
发明人： Ryu Ogiwara , Daisaburo Takashima
摘要： According to one embodiment, a semiconductor memory device includes a memory cell including a variable resistance element, a first circuit including a first resistance element and a first transistor, a first bit line, a second transistor, and a sense circuit. The memory cell and the first circuit are connected to the first bit line. One end and the other end of the second transistor are connected to the first bit line and the sense circuit respectively. During a first operation before reading data of the memory cell a voltage of the first bit line falls to a first voltage and the first and second transistors are turned off in response to a fall of the voltage of the first bit line to the first voltage.
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