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    SEMICONDUCTOR MEMORY DEVICE
    1.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20200279864A1

    公开(公告)日：2020-09-03

    申请号：US16558725

    申请日：2019-09-03

    Applicant: Toshiba Memory Corporation

    Inventor： Ken KOMIYA ,  Takashi ISHIDA ,  Hiroshi KANNO

    IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L29/10 ,  H01L21/74

    Abstract: A semiconductor memory device includes a substrate, gate electrodes arranged in a thickness direction of the substrate, first and second semiconductor layers, a gate insulating film, and a first contact. The first semiconductor layer extends in the thickness direction and faces the gate electrodes. The gate insulating film is between the gate electrodes and the first semiconductor layer. The second semiconductor layer is between the substrate and the gate electrodes and connected to a side surface of the first semiconductor layer in a surface direction. The first contact extends in the thickness direction and electrically connected to the second semiconductor layer. The second semiconductor layer includes a first region in contact with the side surface of the first semiconductor layer and containing P-type impurities, and a first contact region electrically connected to the first contact and having a higher concentration of N-type impurities than the first region.

    NON-VOLATILE MEMORY DEVICE
    2.
    发明申请
    NON-VOLATILE MEMORY DEVICE 审中-公开

    公开(公告)号：US20190267398A1

    公开(公告)日：2019-08-29

    申请号：US16411307

    申请日：2019-05-14

    Applicant: Toshiba Memory Corporation

    Inventor： Takashi ISHIDA ,  Yoshiaki FUKUZUMI ,  Takayuki OKADA ,  Masaki TSUJI

    IPC: H01L27/11582 ,  H01L27/1157 ,  H01L29/10 ,  H01L29/423 ,  H01L27/11565

    Abstract: According to an embodiment, a non-volatile memory device includes first electrodes stacked on an underlying layer, a second electrode provided on the first electrodes, a semiconductor layer extending in a first direction from the underlying layer to the second electrode, and a memory film provided between each of the first electrodes and the semiconductor layer. The semiconductor layer includes a first portion adjacent to the first electrodes and a second portion adjacent to the second electrode. The second portion has a thickness thinner than a thickness of the first portion in a second direction perpendicular to the first direction.

    NON-VOLATILE MEMORY DEVICE
    5.
    发明申请
    NON-VOLATILE MEMORY DEVICE 有权

    公开(公告)号：US20210111189A1

    公开(公告)日：2021-04-15

    申请号：US17128915

    申请日：2020-12-21

    Applicant: Toshiba Memory Corporation

    Inventor： Takashi ISHIDA ,  Yoshiaki FUKUZUMI ,  Takayuki OKADA ,  Masaki TSUJI

    IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/10 ,  H01L29/423

    Abstract: According to an embodiment, a non-volatile memory device includes first electrodes stacked on an underlying layer, a second electrode provided on the first electrodes, a semiconductor layer extending in a first direction from the underlying layer to the second electrode, and a memory film provided between each of the first electrodes and the semiconductor layer. The semiconductor layer includes a first portion adjacent to the first electrodes and a second portion adjacent to the second electrode. The second portion has a thickness thinner than a thickness of the first portion in a second direction perpendicular to the first direction.

    SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR DRIVING SAME
    6.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR DRIVING SAME 有权

    公开(公告)号：US20180090210A1

    公开(公告)日：2018-03-29

    申请号：US15453058

    申请日：2017-03-08

    Applicant: Toshiba Memory Corporation

    Inventor： Takashi ISHIDA

    IPC: G11C16/16 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11573 ,  H01L23/528 ,  H01L23/522 ,  G11C16/04

    CPC classification number: G11C16/16 ,  G11C16/0466 ,  G11C16/0483 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

    Abstract: A semiconductor memory device includes first to fourth electrodes; first and second semiconductor members; a first charge storage member provided between the first semiconductor member and the first electrode; a first interconnect connected to the second electrode side of the first semiconductor member and to the fourth electrode side of the second semiconductor member; and a control circuit. The control circuit sets the first interconnect to a floating state, causes a potential of the third electrode side of the second semiconductor member to increase to a first potential, causes the potential of the third electrode to increase to a second potential lower than the first potential, causes the potential of the second electrode to increase to a third potential lower than the first potential, applies a fourth potential lower than the second and the third potentials to the first electrode, and sets the fourth electrode to a floating state.

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