公开(公告)号：US20210384259A1

公开(公告)日：2021-12-09

申请号：US17407896

申请日：2021-08-20

Applicant: Toshiba Memory Corporation

Inventor： Yusuke KOBAYASHI ,  Yoshihisa IWATA ,  Takeshi SUGIMOTO

IPC: H01L27/24 ,  H01L23/528

Abstract: According to the embodiment, a semiconductor memory device includes a first conductive layer, a second conductive layer, a first memory cell, a second memory cell, a third conductive layer, a first contact, a intermediate memory cell, a fourth conductive layer, a third memory cell, a fifth conductive layer, and a second contact. The third conductive layer is separated from the first conductive layer and the second conductive layer in a third direction crossing a first direction and crossing a second direction and extends in the second direction. The fifth conductive layer is separated from the second conductive layer in the third direction and extends in the second direction. A first length of the second conductive layer along the second direction is shorter than a second length of the fifth conductive layer along the second direction.

公开(公告)号：US20180277201A1

公开(公告)日：2018-09-27

申请号：US15694547

申请日：2017-09-01

Applicant: Toshiba Memory Corporation

Inventor： Megumu HORI ,  Yoshihisa IWATA

IPC: G11C13/00

CPC classification number: G11C13/004 ,  G11C11/56 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0061 ,  G11C2013/0054 ,  G11C2013/0057

Abstract: A semiconductor memory device includes a first memory cell having a first end connected to a first wiring and a second end connected to a second wiring and a second memory cell having a first end connected to the first wiring and a second end connected to a third wiring. A sense amplifier is configured to: sense a first current flowing in the first wiring when a first voltage is applied to the second and third wirings and a second voltage, larger than the first voltage, is applied to the first wiring; and sense a second current flowing in the first wiring when a third voltage larger than the second voltage is applied to the first wiring, the first voltage to the second wiring, and the second voltage to the third wiring. The sense amplifier reads data according to a difference between the first current and the second current.

公开(公告)号：US20200243606A1

公开(公告)日：2020-07-30

申请号：US16845538

申请日：2020-04-10

Applicant: Toshiba Memory Corporation

Inventor： Yusuke KOBAYASHI ,  Yoshihisa IWATA ,  Takeshi SUGIMOTO

IPC: H01L27/24 ,  H01L23/528

Abstract: According to the embodiment, a semiconductor memory device includes a first conductive layer, a second conductive layer, a first memory cell, a second memory cell, a third conductive layer, a first contact, a intermediate memory cell, a fourth conductive layer, a third memory cell, a fifth conductive layer, and a second contact. The third conductive layer is separated from the first conductive layer and the second conductive layer in a third direction crossing a first direction and crossing a second direction and extends in the second direction. The fifth conductive layer is separated from the second conductive layer in the third direction and extends in the second direction. A first length of the second conductive layer along the second direction is shorter than a second length of the fifth conductive layer along the second direction.

公开(公告)号：US20190189693A1

公开(公告)日：2019-06-20

申请号：US16282482

申请日：2019-02-22

Applicant: Toshiba Memory Corporation

Inventor： Yusuke KOBAYASHI ,  Yoshihisa IWATA ,  Takeshi SUGIMOTO

IPC: H01L27/24 ,  H01L23/528

CPC classification number: H01L27/2481 ,  H01L23/528 ,  H01L27/2436

Abstract: According to the embodiment, a semiconductor memory device includes a first conductive layer, a second conductive layer, a first memory cell, a second memory cell, a third conductive layer, a first contact, a intermediate memory cell, a fourth conductive layer, a third memory cell, a fifth conductive layer, and a second contact. The third conductive layer is separated from the first conductive layer and the second conductive layer in a third direction crossing a first direction and crossing a second direction and extends in the second direction. The fifth conductive layer is separated from the second conductive layer in the third direction and extends in the second direction. A first length of the second conductive layer along the second direction is shorter than a second length of the fifth conductive layer along the second direction.

公开(公告)号：US20180337194A1

公开(公告)日：2018-11-22

申请号：US16047811

申请日：2018-07-27

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Tomoo HISHIDA ,  Yoshihisa IWATA

IPC: H01L27/11582 ,  H01L29/792 ,  G11C5/06 ,  H01L27/11575 ,  H01L27/11568 ,  G11C7/18 ,  H01L23/528 ,  G11C5/02 ,  G11C16/04 ,  G11C8/12 ,  H01L27/10 ,  G11C5/04

CPC classification number: H01L27/11582 ,  G11C5/025 ,  G11C5/04 ,  G11C5/063 ,  G11C7/18 ,  G11C8/12 ,  G11C16/0483 ,  G11C2213/71 ,  H01L23/528 ,  H01L27/10 ,  H01L27/11568 ,  H01L27/11575 ,  H01L29/7926 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor memory device comprises: a semiconductor substrate; a plurality of memory units provided on the semiconductor substrate and each including a plurality of memory cells that are stacked; and a plurality of bit lines formed above each of a plurality of the memory units aligned in a column direction, an alignment pitch in a row direction of the plurality of bit lines being less than an alignment pitch in the row direction of the memory units, and an end of each of the memory units aligned in the column direction being connected to one of the plurality of bit lines formed above the plurality of the memory units aligned in the column direction.

公开(公告)号：US20180175111A1

公开(公告)日：2018-06-21

申请号：US15899465

申请日：2018-02-20

Applicant: Toshiba Memory Corporation

Inventor： Yusuke KOBAYASHI ,  Yoshihisa IWATA ,  Takeshi SUGIMOTO

IPC: H01L27/24 ,  H01L23/528

CPC classification number: H01L27/2481 ,  H01L23/528 ,  H01L27/2436

Abstract: According to the embodiment, a semiconductor memory device includes a first conductive layer, a second conductive layer, a first memory cell, a second memory cell, a third conductive layer, a first contact, a intermediate memory cell, a fourth conductive layer, a third memory cell, a fifth conductive layer, and a second contact. The third conductive layer is separated from the first conductive layer and the second conductive layer in a third direction crossing a first direction and crossing a second direction and extends in the second direction. The fifth conductive layer is separated from the second conductive layer in the third direction and extends in the second direction. A first length of the second conductive layer along the second direction is shorter than a second length of the fifth conductive layer along the second direction.