公开(公告)号：US10153345B2

公开(公告)日：2018-12-11

申请号：US15576740

申请日：2016-06-03

申请人： TOYOTA JIDOSHA KABUSHIKI KAISHA ,  DENSO CORPORATION

发明人： Hidefumi Takaya ,  Shoji Mizuno ,  Yukihiko Watanabe ,  Sachiko Aoi

IPC分类号： H01L29/16 ,  H01L21/02 ,  H01L29/423 ,  H01L29/66 ,  H01L29/739 ,  H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L21/04 ,  H01L29/36

摘要： A method for manufacturing an insulated gate switching device is provided. The method includes: forming a first trench in a surface of a first SiC semiconductor layer; implanting p-type impurities into a bottom surface of the first trench; depositing a second SiC semiconductor layer on an inner surface of the first trench to form a second trench; and forming a gate insulating layer, a gate electrode, a first region and a body region so that the gate insulating layer covers an inner surface of the second trench, the gate electrode is located in the second trench, the first region is of n-type and in contact with the gate insulating layer, the body region is of p-type, separated from the implanted region, and in contact with the gate insulating layer under the first region.

公开(公告)号：US20180182889A1

公开(公告)日：2018-06-28

申请号：US15816697

申请日：2017-11-17

申请人： TOYOTA JIDOSHA KABUSHIKI KAISHA ,  DENSO CORPORATION

发明人： Hidefumi Takaya ,  Yasushi Urakami ,  Yukihiko Watanabe

IPC分类号： H01L29/78 ,  H01L29/16 ,  H01L29/10 ,  H01L29/66

摘要： An n-type drift region, a p-type first body region and a p-type contact region are formed on an SiC substrate by epitaxial growth. An opening is formed within the contact region by etching such that the first body region is exposed through the opening, and a p-type second body region is formed on the first body region exposed through the opening by epitaxial growth. An n-type source region is formed by epitaxial growth, and an opening is formed within a part of the source region located on the contact region by etching such that the contact region is exposed through the opening. A trench is formed by etching such that the trench extends from the source region to the drift region through the opening of the contact region, and a gate insulating film and a gate electrode are formed within the trench.

公开(公告)号：US09847414B2

公开(公告)日：2017-12-19

申请号：US14942547

申请日：2015-11-16

申请人： Toyota Jidosha Kabushiki Kaisha

发明人： Hidefumi Takaya ,  Shinichiro Miyahara ,  Katsuhiro Kutsuki ,  Sachiko Aoi

IPC分类号： H01L29/732 ,  H01L29/78 ,  H01L29/66 ,  H01L21/762 ,  H01L29/423 ,  H01L29/06

CPC分类号： H01L29/7813 ,  H01L21/76237 ,  H01L29/0623 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/66734

摘要： A semiconductor device provided herein includes a trench in which a gate insulating layer (GIL) and a gate electrode are located. A step is provided in a lateral surface of the trench. The step surface descends toward a center of the trench. First and second regions are of a first conductivity type. A body region, a lateral region and a bottom region are of a second conductivity type. The first region, a body region, and the second region are in contact with the GIL at the upper lateral surface of the trench. The second region is in contact with the GIL at the lower lateral surface of the trench. A lateral region is in contact with the GIL at the lower lateral surface. A bottom region is in contact with the GIL at the bottom surface of the trench.

公开(公告)号：US09543428B2

公开(公告)日：2017-01-10

申请号：US14400365

申请日：2013-06-06

申请人： DENSO CORPORATION ,  TOYOTA JIDOSHA KABUSHIKI KAISHA ,  Masahiro Sugimoto ,  Hidefumi Takaya ,  Akitaka Soeno ,  Jun Morimoto

发明人： Yuichi Takeuchi ,  Naohiro Suzuki ,  Masahiro Sugimoto ,  Hidefumi Takaya ,  Akitaka Soeno ,  Jun Morimoto ,  Narumasa Soejima ,  Yukihiko Watanabe

IPC分类号： H01L29/78 ,  H01L29/16 ,  H01L21/82 ,  H01L29/66 ,  H01L29/10 ,  H01L29/872 ,  H01L21/04 ,  H01L21/306 ,  H01L21/308 ,  H01L29/423 ,  H01L29/417 ,  H01L29/06 ,  H01L29/08 ,  H01L29/861

CPC分类号： H01L29/7811 ,  H01L21/046 ,  H01L21/0475 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/761 ,  H01L21/8213 ,  H01L29/0615 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0661 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/157 ,  H01L29/158 ,  H01L29/1608 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66068 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7813 ,  H01L29/861 ,  H01L29/872

摘要： An SiC semiconductor device has a p type region including a low concentration region and a high concentration region filled in a trench formed in a cell region. A p type column is provided by the low concentration region, and a p+ type deep layer is provided by the high concentration region. Thus, since a SJ structure can be made by the p type column and the n type column provided by the n type drift layer, an on-state resistance can be reduced. As a drain potential can be blocked by the p+ type deep layer, at turnoff, an electric field applied to the gate insulation film can be alleviated and thus breakage of the gate insulation film can be restricted. Therefore, the SiC semiconductor device can realize the reduction of the on-state resistance and the restriction of breakage of the gate insulation film.

摘要翻译： SiC半导体器件具有包含低浓度区域和填充在形成于单元区域的沟槽中的高浓度区域的p型区域。 由低浓度区域提供p型列，并且由高浓度区域提供p +型深层。 因此，由于可以通过由n型漂移层提供的p型列和n型列来形成SJ结构，所以可以降低导通电阻。 由于漏极电位可以被p +型深层阻挡，所以在关断时，施加到栅极绝缘膜的电场可以减轻，从而可以限制栅极绝缘膜的破裂。 因此，SiC半导体器件可以实现导通电阻的降低和栅极绝缘膜的破损的限制。

公开(公告)号：US09214526B2

公开(公告)日：2015-12-15

申请号：US14557662

申请日：2014-12-02

申请人： TOYOTA JIDOSHA KABUSHIKI KAISHA ,  DENSO CORPORATION

发明人： Hidefumi Takaya ,  Yukihiko Watanabe ,  Sachiko Aoi ,  Atsuya Akiba

IPC分类号： H01L29/78 ,  H01L29/423

CPC分类号： H01L29/4236 ,  H01L29/0623 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/66734 ,  H01L29/7813

摘要： A semiconductor device includes: a drift layer having a first conductivity type; a body layer having a second conductivity type; a first semiconductor region having the first conductivity type; a gate insulation film; a trench gate electrode; a first main electrode; a second semiconductor region having the second conductivity type; and a conductor region. The first main electrode is electrically connected with the body layer and the first semiconductor region. The second semiconductor region is disposed on a bottom part of the gate trench, and is surrounded by the drift layer. The conductor region is configured to electrically connect the first main electrode with the second semiconductor region and is configured to equalize, when the semiconductor device is in an off-state, a potential of the second semiconductor region and a potential of the first main electrode.

摘要翻译： 半导体器件包括：具有第一导电类型的漂移层; 具有第二导电类型的主体层; 具有第一导电类型的第一半导体区; 栅极绝缘膜; 沟槽栅电极; 第一主电极; 具有第二导电类型的第二半导体区; 和导体区域。 第一主电极与主体层和第一半导体区电连接。 第二半导体区域设置在栅极沟槽的底部，被漂移层包围。 导体区域被配置为将第一主电极与第二半导体区域电连接，并且被配置为当半导体器件处于截止状态时使第二半导体区域的电位和第一主电极的电位相等。

公开(公告)号：US10134593B2

公开(公告)日：2018-11-20

申请号：US15570841

申请日：2016-04-05

申请人： DENSO CORPORATION ,  TOYOTA JIDOSHA KABUSHIKI KAISHA

发明人： Takeshi Endo ,  Atsuya Akiba ,  Yuichi Takeuchi ,  Hidefumi Takaya ,  Sachiko Aoi

IPC分类号： H01L29/00 ,  H01L21/20 ,  H01L21/265 ,  H01L29/78 ,  H01L29/06 ,  H01L29/12 ,  H01L29/08 ,  H01L29/16 ,  H01L21/00 ,  H01L21/04

摘要： A semiconductor device includes: a substrate having a cell region with a semiconductor element and an outer peripheral region; and a drift layer on the substrate. The semiconductor element includes a base region, a source region, a trench gate structure, a deep layer deeper than a gate trench, a source electrode, and a drain electrode. The outer peripheral region has a recess portion in which the drift layer are exposed, and a guard ring layer. The guard ring layer includes multiple guard ring trenches having a frame shape, surrounding the cell region and arranged on an exposed surface of the drift layer, and a first guard ring in the guard ring trenches. Each of the linear deep trenches has a width equal to a width of each of the linear guard ring trenches.

公开(公告)号：US09853139B2

公开(公告)日：2017-12-26

申请号：US15124326

申请日：2015-02-10

申请人： TOYOTA JIDOSHA KABUSHIKI KAISHA ,  DENSO CORPORATION

发明人： Hidefumi Takaya ,  Jun Saito ,  Akitaka Soeno ,  Toshimasa Yamamoto ,  Narumasa Soejima

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/12 ,  H01L21/761 ,  H01L29/10 ,  H01L29/40 ,  H01L29/66 ,  H01L29/423

CPC分类号： H01L29/7811 ,  H01L21/761 ,  H01L29/06 ,  H01L29/0623 ,  H01L29/0661 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/12 ,  H01L29/408 ,  H01L29/4236 ,  H01L29/66734 ,  H01L29/7813

摘要： A semiconductor device provided herein includes: a fourth region of a p-type being in contact with a lower end of the gate trench; a termination trench provided in the front surface in a range outside the second region; a lower end p-type region of the p-type being in contact with a lower end of the termination trench; a lateral p-type region of the p-type being in contact with a lateral surface of the termination trench on an outer circumferential side, connected to the lower end p-type region, and exposed on the front surface; and a plurality of guard ring regions provided on the outer circumferential side with respect to the lateral p-type region and exposed on the front surface.

公开(公告)号：US09818860B2

公开(公告)日：2017-11-14

申请号：US15365150

申请日：2016-11-30

申请人： DENSO CORPORATION ,  TOYOTA JIDOSHA KABUSHIKI KAISHA ,  Masahiro Sugimoto ,  Hidefumi Takaya ,  Akitaka Soeno ,  Jun Morimoto

发明人： Yuichi Takeuchi ,  Naohiro Suzuki ,  Masahiro Sugimoto ,  Hidefumi Takaya ,  Akitaka Soeno ,  Jun Morimoto ,  Narumasa Soejima ,  Yukihiko Watanabe

IPC分类号： H01L29/78 ,  H01L29/16 ,  H01L21/82 ,  H01L29/417 ,  H01L29/66 ,  H01L29/10 ,  H01L29/872 ,  H01L21/04 ,  H01L21/306 ,  H01L21/308 ,  H01L29/423 ,  H01L21/761 ,  H01L29/15 ,  H01L29/06 ,  H01L29/08 ,  H01L29/861

CPC分类号： H01L29/7811 ,  H01L21/046 ,  H01L21/0475 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/761 ,  H01L21/8213 ,  H01L29/0615 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0661 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/157 ,  H01L29/158 ,  H01L29/1608 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66068 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7813 ,  H01L29/861 ,  H01L29/872

摘要： An SiC semiconductor device has a p type region including a low concentration region and a high concentration region filled in a trench formed in a cell region. A p type column is provided by the low concentration region, and a p+ type deep layer is provided by the high concentration region. Thus, since a SJ structure can be made by the p type column and the n type column provided by the n type drift layer, an on-state resistance can be reduced. As a drain potential can be blocked by the p+ type deep layer, at turnoff, an electric field applied to the gate insulation film can be alleviated and thus breakage of the gate insulation film can be restricted. Therefore, the SiC semiconductor device can realize the reduction of the on-state resistance and the restriction of breakage of the gate insulation film.

公开(公告)号：US09627248B2

公开(公告)日：2017-04-18

申请号：US15110802

申请日：2015-02-05

申请人： TOYOTA JIDOSHA KABUSHIKI KAISHA

发明人： Jun Saito ,  Kimimori Hamada ,  Akitaka Soeno ,  Hidefumi Takaya ,  Sachiko Aoi ,  Toshimasa Yamamoto

IPC分类号： H01L29/66 ,  H01L21/762 ,  H01L29/06 ,  H01L29/16 ,  H01L29/423 ,  H01L21/761

CPC分类号： H01L21/76229 ,  H01L21/761 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0696 ,  H01L29/1608 ,  H01L29/4236 ,  H01L29/66068 ,  H01L29/7811 ,  H01L29/7813

摘要： An insulating gate type semiconductor device being capable of easily depleting an outer periphery region is provided. The insulating gate type semiconductor device includes: first to fourth outer periphery trenches formed in a front surface of a semiconductor substrate; insulating layers located in the outer periphery trenches; fifth semiconductor regions being of a second conductive type and formed in ranges exposed to bottom surfaces of the outer periphery trenches; and a connection region connecting the fifth semiconductor region exposed to the bottom surface of the second outer periphery trench to the fifth semiconductor region exposed to the bottom surface of the third outer periphery trench. A clearance between the second and third outer periphery trenches is wider than each of a clearance between the first and second outer periphery trenches and a clearance between the third and fourth outer periphery trenches.

公开(公告)号：US20150115286A1

公开(公告)日：2015-04-30

申请号：US14400365

申请日：2013-06-06

申请人： Masahiro SUGIMOTO ,  Hidefumi TAKAYA ,  Akitaka SOENO ,  Jun MORIMOTO ,  DENSO CORPORATION ,  TOYOTA JIDOSHA KABUSHIKI KAISHA

发明人： Yuichi Takeuchi ,  Naohiro Suzuki ,  Masahiro Sugimoto ,  Hidefumi Takaya ,  Akitaka Soeno ,  Jun Morimoto ,  Narumasa Soejima ,  Yukihiko Watanabe

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L21/308 ,  H01L29/10 ,  H01L21/04 ,  H01L21/306 ,  H01L29/66 ,  H01L29/16

CPC分类号： H01L29/7811 ,  H01L21/046 ,  H01L21/0475 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/761 ,  H01L21/8213 ,  H01L29/0615 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0661 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/157 ,  H01L29/158 ,  H01L29/1608 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66068 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7813 ,  H01L29/861 ,  H01L29/872

摘要： An SiC semiconductor device has a p type region including a low concentration region and a high concentration region filled in a trench formed in a cell region. A p type column is provided by the low concentration region, and a p+ type deep layer is provided by the high concentration region. Thus, since a SJ structure can be made by the p type column and the n type column provided by the n type drift layer, an on-state resistance can be reduced. As a drain potential can be blocked by the p+ type deep layer, at turnoff, an electric field applied to the gate insulation film can be alleviated and thus breakage of the gate insulation film can be restricted. Therefore, the SiC semiconductor device can realize the reduction of the on-state resistance and the restriction of breakage of the gate insulation film.

摘要翻译： SiC半导体器件具有包含低浓度区域和填充在形成于单元区域的沟槽中的高浓度区域的p型区域。 由低浓度区域提供p型列，并且由高浓度区域提供p +型深层。 因此，由于可以通过由n型漂移层提供的p型列和n型列来形成SJ结构，所以可以降低导通电阻。 由于漏极电位可以被p +型深层阻挡，所以在关断时，施加到栅极绝缘膜的电场可以减轻，从而可以限制栅极绝缘膜的破裂。 因此，SiC半导体器件可以实现导通电阻的降低和栅极绝缘膜的破损的限制。