公开(公告)号：US20070238228A1

公开(公告)日：2007-10-11

申请号：US11393436

申请日：2006-03-29

申请人： Ta-Jung Su ,  Chin-Tzu Kao ,  Chia-Che Hsu

发明人： Ta-Jung Su ,  Chin-Tzu Kao ,  Chia-Che Hsu

IPC分类号： H01L21/84

CPC分类号： H01L27/1288 ,  H01L27/1214

摘要： A manufacturing method for a thin film transistor (TFT) is provided. In the manufactured TFT, after a source structure, a drain structure and a channel structure are formed, a first photoresist layer is not removed and a second photoresist is formed on the first photoresist layer through which a semiconductor structure is formed. Further, n-type amorphous silicon, poly silicon or an organic metallic compound is used in replace of the conventional metal to form the source and drain structures so as to reduce step number of manufacturing for the TFT.

摘要翻译： 提供了薄膜晶体管（TFT）的制造方法。 在制造的TFT中，在源极结构形成漏极结构和沟道结构之后，不去除第一光致抗蚀剂层，并且在形成半导体结构的第一光致抗蚀剂层上形成第二光致抗蚀剂。 此外，使用n型非晶硅，多晶硅或有机金属化合物代替常规金属以形成源极和漏极结构，以便减少TFT的制造步骤数量。

公开(公告)号：US07754509B2

公开(公告)日：2010-07-13

申请号：US11393436

申请日：2006-03-29

申请人： Ta-Jung Su ,  Chin-Tzu Kao ,  Chia-Che Hsu

发明人： Ta-Jung Su ,  Chin-Tzu Kao ,  Chia-Che Hsu

IPC分类号： H01L21/00

CPC分类号： H01L27/1288 ,  H01L27/1214

摘要： A manufacturing method for a thin film transistor (TFT) is provided. In the manufactured TFT, after a source structure, a drain structure and a channel structure are formed, a first photoresist layer is not removed and a second photoresist is formed on the first photoresist layer through which a semiconductor structure is formed. Further, n-type amorphous silicon, poly silicon or an organic metallic compound is used in replace of the conventional metal to form the source and drain structures so as to reduce step number of manufacturing for the TFT.

摘要翻译： 提供了薄膜晶体管（TFT）的制造方法。 在制造的TFT中，在源极结构形成漏极结构和沟道结构之后，不去除第一光致抗蚀剂层，并且在形成半导体结构的第一光致抗蚀剂层上形成第二光致抗蚀剂。 此外，使用n型非晶硅，多晶硅或有机金属化合物代替常规金属以形成源极和漏极结构，以便减少TFT的制造步骤数量。

公开(公告)号：US07005332B2

公开(公告)日：2006-02-28

申请号：US11019074

申请日：2004-12-21

申请人： Ying-Ming Wu ,  Ta-Jung Su ,  Yi-Tsai Hsu ,  Chin-Tzu Kao

发明人： Ying-Ming Wu ,  Ta-Jung Su ,  Yi-Tsai Hsu ,  Chin-Tzu Kao

IPC分类号： H01L21/336

CPC分类号： H01L29/66765 ,  H01L27/12 ,  H01L27/124 ,  H01L27/1288 ,  H01L29/458 ,  H01L29/4908

摘要： A TFT fabrication method includes: forming a gate insulation layer, a semiconductor layer and a metal layer on a substrate in sequence, which cover a gate; patterning the metal layer and the semiconductor layer; forming a patterned first passivation layer on the substrate and exposing the patterned metal layer; forming a pixel electrode layer on the substrate to cover the patterned first passivation layer and the patterned metal layer; forming a patterned photoresist layer on the substrate and exposing the pixel electrode layer above the gate; etching the pixel electrode layer and the patterned metal layer to form a patterned pixel electrode layer, a source, and a drain to form a channel region on the patterned semiconductor layer; forming a second passivation layer on the substrate; and removing the patterned photoresist layer to lift off the second passivation layer, thereby exposing the patterned pixel electrode layer.

摘要翻译： TFT制造方法包括：依次在基板上形成覆盖栅极的栅极绝缘层，半导体层和金属层; 图案化金属层和半导体层; 在所述衬底上形成图案化的第一钝化层并暴露所述图案化的金属层; 在所述衬底上形成像素电极层以覆盖所述图案化的第一钝化层和所述图案化的金属层; 在衬底上形成图案化的光致抗蚀剂层，并使栅极上方的像素电极层曝光; 蚀刻像素电极层和图案化的金属层以形成图案化的像素电极层，源极和漏极，以在图案化的半导体层上形成沟道区域; 在所述衬底上形成第二钝化层; 以及去除图案化的光致抗蚀剂层以剥离第二钝化层，从而暴露图案化的像素电极层。

公开(公告)号：US07049163B1

公开(公告)日：2006-05-23

申请号：US10907003

申请日：2005-03-16

申请人： Chin-Tzu Kao ,  Ta-Jung Su ,  Fu-Liang Lin

发明人： Chin-Tzu Kao ,  Ta-Jung Su ,  Fu-Liang Lin

IPC分类号： H01L21/28

CPC分类号： H01L27/1288 ,  H01L27/124

摘要： A manufacture method of a pixel structure is provided. A gate is formed over a substrate, and a gate insulator layer is formed over the substrate covering the gate. A semiconductor layer is formed over the gate insulator layer and a metal layer is formed over the semiconductor layer. A first mask layer is formed on the metal layer, and the metal layer is patterned to form a source/drain by using the first mask layer as etching mask. Afterward, a second mask layer is formed on the first mask layer and further covers a region between the source/drain. The semiconductor layer is patterned by using the first and second mask layers as etching mask, and then the first and second mask layers are removed. A passivation layer is formed over the substrate. A pixel electrode is formed on the passivation layer. The pixel electrode is electrically connected with the drain.

摘要翻译： 提供了像素结构的制造方法。 栅极形成在衬底上，并且栅极绝缘体层形成在覆盖栅极的衬底上。 半导体层形成在栅极绝缘体层上方，并且在半导体层上形成金属层。 在金属层上形成第一掩模层，通过使用第一掩模层作为蚀刻掩模，将金属层图案化以形成源极/漏极。 之后，在第一掩模层上形成第二掩模层，并进一步覆盖源极/漏极之间的区域。 通过使用第一和第二掩模层作为蚀刻掩模来对半导体层进行构图，然后去除第一和第二掩模层。 钝化层形成在衬底上。 在钝化层上形成像素电极。 像素电极与漏极电连接。

公开(公告)号：US20060079036A1

公开(公告)日：2006-04-13

申请号：US10711835

申请日：2004-10-08

申请人： Ta-Jung Su ,  Chin-Tzu Kao ,  Mi-Cheng Lai ,  Yi-Tsai Hsu

发明人： Ta-Jung Su ,  Chin-Tzu Kao ,  Mi-Cheng Lai ,  Yi-Tsai Hsu

IPC分类号： H01L21/4763

CPC分类号： H01L29/4908 ,  H01L29/66765

摘要： A method of manufacturing a gate, a thin film transistor and a pixel. First, a patterned mask layer is formed on a substrate. The mask layer exposes an area for forming the gate. A gate is formed on the exposed area of the substrate and then the mask layer is removed. The method produces a gate having a well-defined profile. When the method is applied to form a transistor or a pixel, coverage of a subsequently form film layer is improved and point discharge is prevented.

摘要翻译： 一种制造栅极，薄膜晶体管和像素的方法。 首先，在基板上形成图案化的掩模层。 掩模层露出用于形成栅极的区域。 在衬底的暴露区域上形成栅极，然后去除掩模层。 该方法产生具有明确限定的轮廓的门。 当该方法用于形成晶体管或像素时，随后形成的膜层的覆盖率得到改善，并且防止点放电。

公开(公告)号：US20060008952A1

公开(公告)日：2006-01-12

申请号：US11019074

申请日：2004-12-21

申请人： Ying-Ming Wu ,  Ta-Jung Su ,  Yi-Tsai Hsu ,  Chin-Tzu Kao

发明人： Ying-Ming Wu ,  Ta-Jung Su ,  Yi-Tsai Hsu ,  Chin-Tzu Kao

IPC分类号： H01L21/00

CPC分类号： H01L29/66765 ,  H01L27/12 ,  H01L27/124 ,  H01L27/1288 ,  H01L29/458 ,  H01L29/4908

摘要： A TFT fabrication method includes: forming a gate insulation layer, a semiconductor layer and a metal layer on a substrate in sequence, which cover a gate; patterning the metal layer and the semiconductor layer; forming a patterned first passivation layer on the substrate and exposing the patterned metal layer; forming a pixel electrode layer on the substrate to cover the patterned first passivation layer and the patterned metal layer; forming a patterned photoresist layer on the substrate and exposing the pixel electrode layer above the gate; etching the pixel electrode layer and the patterned metal layer to form a patterned pixel electrode layer, a source, and a drain to form a channel region on the patterned semiconductor layer; forming a second passivation layer on the substrate; and removing the patterned photoresist layer to lift off the second passivation layer, thereby exposing the patterned pixel electrode layer.

摘要翻译： TFT制造方法包括：依次在基板上形成覆盖栅极的栅极绝缘层，半导体层和金属层; 图案化金属层和半导体层; 在所述衬底上形成图案化的第一钝化层并暴露所述图案化的金属层; 在所述衬底上形成像素电极层以覆盖所述图案化的第一钝化层和所述图案化的金属层; 在衬底上形成图案化的光致抗蚀剂层，并使栅极上方的像素电极层曝光; 蚀刻像素电极层和图案化的金属层以形成图案化的像素电极层，源极和漏极，以在图案化的半导体层上形成沟道区域; 在所述衬底上形成第二钝化层; 以及去除图案化的光致抗蚀剂层以剥离第二钝化层，从而暴露图案化的像素电极层。

公开(公告)号：US08501552B2

公开(公告)日：2013-08-06

申请号：US13369272

申请日：2012-02-08

申请人： Chin-Tzu Kao ,  Yu-Tsung Lee

发明人： Chin-Tzu Kao ,  Yu-Tsung Lee

IPC分类号： H01L21/84

CPC分类号： H01L27/1288

摘要： A pixel structure includes a substrate; a scan line; a gate electrode; an insulating layer disposed on the scan line, the gate electrode and the substrate; a channel and a data line disposed on the insulating layer; a source electrode and a drain electrode disposed on the channel; a passivation layer; a pixel electrode and a connecting electrode. The data line does not overlap the scan line. The passivation layer disposed on the source electrode and the drain electrode includes a first contact hole partially exposing the drain electrode, and a plurality of second contact holes partially exposing the data line or the scan line. The pixel electrode disposed on the passivation layer is electrically connected to the drain electrode through the first contact hole. Furthermore, the connecting electrode disposed on the passivation layer is electrically connected to the data line or the scan line through the second contact holes.

摘要翻译： 像素结构包括基板; 扫描线 栅电极; 布置在所述扫描线上的绝缘层，所述栅电极和所述基板; 设置在绝缘层上的通道和数据线; 设置在通道上的源电极和漏电极; 钝化层; 像素电极和连接电极。 数据线与扫描线不重叠。 设置在源电极和漏电极上的钝化层包括部分地暴露漏电极的第一接触孔和部分地暴露数据线或扫描线的多个第二接触孔。 设置在钝化层上的像素电极通过第一接触孔电连接到漏电极。 此外，设置在钝化层上的连接电极通过第二接触孔电连接到数据线或扫描线。

公开(公告)号：US20130175532A1

公开(公告)日：2013-07-11

申请号：US13454088

申请日：2012-04-24

申请人： Chi-Ming Chiou ,  Yu-Tsung Lee ,  Chin-Tzu Kao

发明人： Chi-Ming Chiou ,  Yu-Tsung Lee ,  Chin-Tzu Kao

IPC分类号： H01L29/786 ,  H01L21/02

CPC分类号： H01L27/1288 ,  H01L27/124 ,  H01L29/66742 ,  H01L29/66765

摘要： A method for manufacturing a pixel structure is provided. A thin film transistor is formed on a substrate and an insulating layer is formed to cover the substrate and the thin film transistor. The insulating layer is patterned by a half-tone mask to form a protruding pattern, a sunken pattern connecting the protruding pattern, and a contact window inside the sunken pattern. A transparent conductive layer is formed to cover the protruding pattern and the sunken pattern, and filled in the contact window. A passivation layer is formed to cover the transparent conductive layer. A pixel electrode pattern is formed from the transparent conductive layer by removing a part of the passivation layer located on the protruding pattern, a part of the transparent conductive layer on the protruding pattern, and a part of the passivation layer located within the contact window. A pixel structure manufactured by the method is provided.

摘要翻译： 提供了一种用于制造像素结构的方法。 在基板上形成薄膜晶体管，形成绝缘层以覆盖基板和薄膜晶体管。 通过半色调掩模对绝缘层进行图案化以形成突出图案，连接突出图案的凹陷图案和凹陷图案内的接触窗口。 形成透明导电层以覆盖突出图案和凹陷图案，并填充在接触窗中。 形成钝化层以覆盖透明导电层。 通过去除位于突出图案上的钝化层的一部分，突出图案上的透明导电层的一部分和位于接触窗内部的钝化层的一部分，由透明导电层形成像素电极图案。 提供了通过该方法制造的像素结构。

公开(公告)号：US20130119385A1

公开(公告)日：2013-05-16

申请号：US13369272

申请日：2012-02-08

申请人： Chin-Tzu Kao ,  Yu-Tsung Lee

发明人： Chin-Tzu Kao ,  Yu-Tsung Lee

IPC分类号： H01L33/02

CPC分类号： H01L27/1288

摘要： A pixel structure includes a substrate; a scan line; a gate electrode; an insulating layer disposed on the scan line, the gate electrode and the substrate; a channel and a data line disposed on the insulating layer; a source electrode and a drain electrode disposed on the channel; a passivation layer; a pixel electrode and a connecting electrode. The data line does not overlap the scan line. The passivation layer disposed on the source electrode and the drain electrode includes a first contact hole partially exposing the drain electrode, and a plurality of second contact holes partially exposing the data line or the scan line. The pixel electrode disposed on the passivation layer is electrically connected to the drain electrode through the first contact hole. Furthermore, the connecting electrode disposed on the passivation layer is electrically connected to the data line or the scan line through the second contact holes.

摘要翻译： 像素结构包括基板; 扫描线 栅电极; 布置在所述扫描线上的绝缘层，所述栅电极和所述基板; 设置在绝缘层上的通道和数据线; 设置在通道上的源电极和漏电极; 钝化层; 像素电极和连接电极。 数据线与扫描线不重叠。 设置在源电极和漏电极上的钝化层包括部分地暴露漏电极的第一接触孔和部分地暴露数据线或扫描线的多个第二接触孔。 设置在钝化层上的像素电极通过第一接触孔电连接到漏电极。 此外，设置在钝化层上的连接电极通过第二接触孔电连接到数据线或扫描线。

公开(公告)号：US07071045B2

公开(公告)日：2006-07-04

申请号：US10839170

申请日：2004-05-06

申请人： Ying-Ming Wu ,  Yi-Tsai Hsu ,  Chin-Tzu Kao ,  Yung-Hsin Wu ,  Jui-chung Chang

发明人： Ying-Ming Wu ,  Yi-Tsai Hsu ,  Chin-Tzu Kao ,  Yung-Hsin Wu ,  Jui-chung Chang

IPC分类号： H01L21/336

CPC分类号： H01L27/1288 ,  H01L27/1214 ,  H01L29/66765

摘要： A process of producing a thin film transistor includes forming a gate line on a substrate by first exposure and development processes. A source electrode, a drain electrode and a semiconductor channel are formed by second exposure and development processes. An island-shaped transistor is formed by third exposure and development processes. A protection layer with a contact hole therein is formed by fourth exposure and development processes. A pixel electrode is formed by fifth exposure and development processes to connect to the contact hole.

摘要翻译： 制造薄膜晶体管的工艺包括通过第一曝光和显影工艺在衬底上形成栅极线。 通过第二曝光和显影处理形成源电极，漏电极和半导体沟道。 通过第三曝光和显影处理形成岛状晶体管。 通过第四曝光和显影处理形成其中具有接触孔的保护层。 通过第五曝光和显影处理形成像素电极以连接到接触孔。