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    Method of manufacturing semiconductor device having stress creating layer
    3.
    发明授权
    Method of manufacturing semiconductor device having stress creating layer 有权
    具有应力产生层的半导体器件的制造方法

    公开(公告)号：US08409947B2

    公开(公告)日：2013-04-02

    申请号：US12693080

    申请日：2010-01-25

    申请人： Jin-bum Kim ,  Wook-je Kim ,  Yu-gyun Shin ,  Kwan-heum Lee ,  Sun-ghil Lee

    发明人： Jin-bum Kim ,  Wook-je Kim ,  Yu-gyun Shin ,  Kwan-heum Lee ,  Sun-ghil Lee

    IPC分类号： H01L21/8238

    CPC分类号： H01L29/7848 ,  H01L21/26513 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636

    摘要： Provided is a simplified method of manufacturing a semiconductor device having a stress creating layer. A first conductive first impurity region is formed on a semiconductor substrate on both sides of a first gate of a first area of the semiconductor substrate, and a second conductive second impurity region is formed on the semiconductor substrate on both sides of a second gate of a second area. First and second spacers are formed on sidewalls of the first and second gates, respectively. First and second semiconductor layers are formed in portions of the semiconductor substrate so as to contact the first and second impurity regions, respectively. The second semiconductor layer is removed. First and second barrier layers are formed in the first and second contact holes of the insulation layer, respectively.

    摘要翻译： 提供了一种制造具有应力产生层的半导体器件的简化方法。 在半导体衬底的第一区域的第一栅极的两侧上的半导体衬底上形成第一导电第一杂质区，并且在半导体衬底的第二栅极的两侧的半导体衬底上形成第二导电第二杂质区 第二区。 第一和第二间隔物分别形成在第一和第二栅极的侧壁上。 第一半导体层和第二半导体层分别形成在半导体衬底的部分中，以分别接触第一和第二杂质区。 去除第二半导体层。 第一和第二阻挡层分别形成在绝缘层的第一和第二接触孔中。

    Method of manufacturing semiconductor device
    4.
    发明授权
    Method of manufacturing semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US08361860B2

    公开(公告)日：2013-01-29

    申请号：US12656130

    申请日：2010-01-19

    申请人： Jin-bum Kim ,  Wook-je Kim ,  Kwan-heum Lee ,  Yu-gyun Shin ,  Sun-ghil Lee

    发明人： Jin-bum Kim ,  Wook-je Kim ,  Kwan-heum Lee ,  Yu-gyun Shin ,  Sun-ghil Lee

    IPC分类号： H01L21/8242

    CPC分类号： H01L21/7687 ,  H01L27/10855 ,  H01L28/91

    摘要： A method of manufacturing a semiconductor device may include forming a first interlayer insulation layer on a substrate including at least one gate structure formed thereon, the substrate having a plurality of source/drain regions formed on both sides of the at least one gate structure, forming at least one buried contact plug on at least one of the plurality of source/drain regions and in the first interlayer insulation layer, forming a second interlayer insulation layer on the first interlayer insulation layer and the at least one buried contact plug, exposing the at least one buried contact plug in the second interlayer insulation layer by forming at least one contact hole, implanting ions in the at least one contact hole in order to create an amorphous upper portion of the at least one buried contact plug, depositing a lower electrode layer on the second interlayer insulation layer and the at least one contact hole, and forming a metal silicide layer in the amorphous upper portion of the at least one buried contact plug.

    摘要翻译： 制造半导体器件的方法可以包括在包括形成在其上的至少一个栅极结构的衬底上形成第一层间绝缘层，所述衬底具有形成在所述至少一个栅极结构的两侧上的多个源/漏区，形成 在所述多个源极/漏极区域和所述第一层间绝缘层中的至少一个上的至少一个埋置的接触插塞，在所述第一层间绝缘层和所述至少一个埋置的接触插塞上形成第二层间绝缘层， 通过形成至少一个接触孔，在所述至少一个接触孔中注入离子，以形成所述至少一个埋入接触插塞的非晶体上部，沉积下部电极层 在所述第二层间绝缘层和所述至少一个接触孔上，并且在所述非晶体上部形成金属硅化物层 的所述至少一个埋入式接触插塞。

    SEMICONDUCTOR DEVICE
    5.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开
    半导体器件

    公开(公告)号：US20110266627A1

    公开(公告)日：2011-11-03

    申请号：US13096311

    申请日：2011-04-28

    申请人： Seung-hun Lee ,  Byeong-chan Lee ,  Sung-kwan Kang ,  Keum-seok Park ,  Yu-gyun Shin ,  Sun-ghil Lee

    发明人： Seung-hun Lee ,  Byeong-chan Lee ,  Sung-kwan Kang ,  Keum-seok Park ,  Yu-gyun Shin ,  Sun-ghil Lee

    IPC分类号： H01L27/092 ,  H01L27/085

    CPC分类号： H01L21/823481 ,  H01L21/823878

    摘要： A semiconductor device includes a semiconductor substrate including a plurality of active areas defined by a device isolation layer, a gate line structure crossing the plurality of active areas, a buffer insulation layer on the semiconductor substrate, the buffer insulation layer contacting a portion of a side of the gate line structure, a contact etching stopper layer on the buffer insulation layer, and a contact plug passing through the buffer insulation layer and the contact etching stopper layer to be connected to the plurality of active areas.

    摘要翻译： 半导体器件包括半导体衬底，其包括由器件隔离层限定的多个有源区，与多个有源区交叉的栅极线结构，半导体衬底上的缓冲绝缘层，缓冲绝缘层接触一侧的一部分 栅极线结构，缓冲绝缘层上的接触蚀刻停止层以及通过缓冲绝缘层和接触蚀刻阻挡层的接触插塞，以连接到多个有源区。

    Method of Manufacturing Semiconductor Device Having Stress Creating Layer
    6.
    发明申请
    Method of Manufacturing Semiconductor Device Having Stress Creating Layer 有权
    制造具有应力创造层的半导体器件的方法

    公开(公告)号：US20100197092A1

    公开(公告)日：2010-08-05

    申请号：US12693080

    申请日：2010-01-25

    申请人： Jin-bum Kim ,  Wook-je Kim ,  Yu-gyun Shin ,  Kwan-heum Lee ,  Sun-Ghil Lee

    发明人： Jin-bum Kim ,  Wook-je Kim ,  Yu-gyun Shin ,  Kwan-heum Lee ,  Sun-Ghil Lee

    IPC分类号： H01L21/8238 ,  H01L21/20

    CPC分类号： H01L29/7848 ,  H01L21/26513 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636

    摘要： Provided is a simplified method of manufacturing a semiconductor device having a stress creating layer. A first conductive first impurity region is formed on a semiconductor substrate on both sides of a first gate of a first area of the semiconductor substrate, and a second conductive second impurity region is formed on the semiconductor substrate on both sides of a second gate of a second area. First and second spacers are formed on sidewalls of the first and second gates, respectively. First and second semiconductor layers are formed in portions of the semiconductor substrate so as to contact the first and second impurity regions, respectively. The second semiconductor layer is removed. First and second barrier layers are formed in the first and second contact holes of the insulation layer, respectively.

    摘要翻译： 提供了一种制造具有应力产生层的半导体器件的简化方法。 在半导体衬底的第一区域的第一栅极的两侧上的半导体衬底上形成第一导电第一杂质区，并且在半导体衬底的第二栅极的两侧的半导体衬底上形成第二导电第二杂质区 第二区。 第一和第二间隔物分别形成在第一和第二栅极的侧壁上。 第一半导体层和第二半导体层分别形成在半导体衬底的部分中，以分别接触第一和第二杂质区。 去除第二半导体层。 第一和第二阻挡层分别形成在绝缘层的第一和第二接触孔中。

    Method of manufacturing semiconductor device
    7.
    发明申请
    Method of manufacturing semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US20100330758A1

    公开(公告)日：2010-12-30

    申请号：US12656130

    申请日：2010-01-19

    申请人： Jin-bum Kim ,  Wook-je Kim ,  Kwan-heum Lee ,  Yu-gyun Shin ,  Sun-ghil Lee

    发明人： Jin-bum Kim ,  Wook-je Kim ,  Kwan-heum Lee ,  Yu-gyun Shin ,  Sun-ghil Lee

    IPC分类号： H01L21/8242 ,  H01L21/283

    CPC分类号： H01L21/7687 ,  H01L27/10855 ,  H01L28/91

    摘要： A method of manufacturing a semiconductor device may include forming a first interlayer insulation layer on a substrate including at least one gate structure formed thereon, the substrate having a plurality of source/drain regions formed on both sides of the at least one gate structure, forming at least one buried contact plug on at least one of the plurality of source/drain regions and in the first interlayer insulation layer, forming a second interlayer insulation layer on the first interlayer insulation layer and the at least one buried contact plug, exposing the at least one buried contact plug in the second interlayer insulation layer by forming at least one contact hole, implanting ions in the at least one contact hole in order to create an amorphous upper portion of the at least one buried contact plug, depositing a lower electrode layer on the second interlayer insulation layer and the at least one contact hole, and forming a metal silicide layer in the amorphous upper portion of the at least one buried contact plug.

    摘要翻译： 制造半导体器件的方法可以包括在包括形成在其上的至少一个栅极结构的衬底上形成第一层间绝缘层，所述衬底具有形成在所述至少一个栅极结构的两侧上的多个源/漏区，形成 在所述多个源极/漏极区域和所述第一层间绝缘层中的至少一个上的至少一个埋置的接触插塞，在所述第一层间绝缘层和所述至少一个埋置的接触插塞上形成第二层间绝缘层， 通过形成至少一个接触孔，在所述至少一个接触孔中注入离子，以形成所述至少一个埋入接触插塞的非晶体上部，沉积下部电极层 在所述第二层间绝缘层和所述至少一个接触孔上，并且在所述非晶体上部形成金属硅化物层 的所述至少一个埋入式接触插塞。

    Trench isolation method for semiconductor device
    9.
    发明授权
    Trench isolation method for semiconductor device 失效
    半导体器件的沟槽隔离方法

    公开(公告)号：US6121110A

    公开(公告)日：2000-09-19

    申请号：US124093

    申请日：1998-07-29

    申请人： Soo-jin Hong ,  Yu-gyun Shin ,  Han-sin Lee ,  Hyun-cheol Choe

    发明人： Soo-jin Hong ,  Yu-gyun Shin ,  Han-sin Lee ,  Hyun-cheol Choe

    IPC分类号： H01L21/76 ,  H01L21/762

    CPC分类号： H01L21/76224

    摘要： A trench isolation method is provided. In the trench isolation method, a pad oxide film, an oxidative film and an etching mask film are formed on a semiconductor substrate in sequence, and then a trench is formed in a field region of the semiconductor substrate. A oxide film is formed at the inner wall of the trench and the side walls of the oxidative film by oxidizing the semiconductor substrate. After filling the trench with a dielectric material, the pad oxide film, oxidative film and etching mask film formed in the active region are removed.

    摘要翻译： 提供沟槽隔离方法。 在沟槽隔离方法中，顺序地在半导体衬底上形成衬垫氧化膜，氧化膜和蚀刻掩模膜，然后在半导体衬底的场区域中形成沟槽。 通过氧化半导体衬底，在沟槽的内壁和氧化膜的侧壁上形成氧化膜。 在用电介质材料填充沟槽之后，去除在活性区域中形成的衬垫氧化膜，氧化膜和蚀刻掩模膜。

    Device isolation method of semiconductor device
    10.
    发明授权
    Device isolation method of semiconductor device 失效
    半导体器件的器件隔离方法

    公开(公告)号：US5641705A

    公开(公告)日：1997-06-24

    申请号：US470914

    申请日：1995-06-06

    申请人： Dong-ho Ahn ,  Seong-joon Ahn ,  Yu-gyun Shin ,  Yun-gi Kim

    发明人： Dong-ho Ahn ,  Seong-joon Ahn ,  Yu-gyun Shin ,  Yun-gi Kim

    IPC分类号： H01L21/316 ,  H01L21/32 ,  H01L21/76 ,  H01L21/762

    CPC分类号： H01L21/76205 ,  H01L21/32

    摘要： In a device isolation method for a semiconductor device, after a pad oxide layer and a nitride layer are formed on a semiconductor substrate, the nitride layer located above the device isolation region is removed. An undercut is formed under the nitride by partially etching the pad oxide layer. After a first oxide layer is formed on the exposed substrate and a polysilicon spacer is formed on the sidewalls of the nitride layer, a void is formed in the oxide layer under the nitride layer which is formed on the active region by oxidizing the resultant structure in which the polysilicon spacer is formed at a temperature above 950.degree. C. Thus, good cell definition and stable device isolation can be realized, while solving the typical problem of conventional LOCOS methods by forming the void intentionally in the pad oxide layer thickened by bird's beak punch through.

    摘要翻译： 在半导体器件的器件隔离方法中，在衬底氧化物层和氮化物层形成在半导体衬底上之后，去除位于器件隔离区上方的氮化物层。 通过部分蚀刻衬垫氧化物层，在氮化物之下形成底切。 在暴露的基板上形成第一氧化物层并在氮化物层的侧壁上形成多晶硅间隔物之后，在形成于有源区上的氮化物层下面的氧化物层中形成空穴， 其中多晶硅间隔物在高于950℃的温度下形成。因此，通过在通过鸟喙加厚的垫氧化物层中有意地形成空穴来解决常规LOCOS方法的典型问题，可以实现良好的电池定义和稳定的器件隔离 穿透